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-rw-r--r--src/arch/arm/isa/templates/mem.isa8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 2ccda65e1..871378f3f 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1122,7 +1122,7 @@ def template LoadRegConstructor {{
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
- if (_dest == INTREG_PC) {
+ if (_dest == INTREG_PC && !isFloating()) {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_shiftAmt, _shiftType, _index);
@@ -1156,7 +1156,7 @@ def template LoadRegConstructor {{
}
#else
- if (_dest == INTREG_PC) {
+ if (_dest == INTREG_PC && !isFloating()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)
@@ -1185,7 +1185,7 @@ def template LoadImmConstructor {{
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
- if (_dest == INTREG_PC) {
+ if (_dest == INTREG_PC && !isFloating()) {
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_imm);
uops[0]->setDelayedCommit();
@@ -1208,7 +1208,7 @@ def template LoadImmConstructor {{
uops[1]->setLastMicroop();
}
#else
- if (_dest == INTREG_PC) {
+ if (_dest == INTREG_PC && !isFloating()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)