diff options
Diffstat (limited to 'src/arch/arm/utility.cc')
| -rw-r--r-- | src/arch/arm/utility.cc | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 73537a89c..924024d0e 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -225,9 +225,7 @@ longDescFormatInUse(ThreadContext *tc) RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc) { - CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); - const ExceptionLevel current_el = - opModeToEL((OperatingMode) (uint8_t) cpsr.mode); + const ExceptionLevel current_el = currEL(tc); const bool is_secure = isSecureBelowEL3(tc); @@ -356,7 +354,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el) bool isBigEndian64(ThreadContext *tc) { - switch (opModeToEL(currOpMode(tc))) { + switch (currEL(tc)) { case EL3: return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee; case EL2: @@ -820,7 +818,7 @@ decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, bool SPAlignmentCheckEnabled(ThreadContext* tc) { - switch (opModeToEL(currOpMode(tc))) { + switch (currEL(tc)) { case EL3: return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa; case EL2: |