diff options
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 8 | ||||
| -rw-r--r-- | src/arch/mips/registers.hh | 2 | ||||
| -rw-r--r-- | src/arch/mips/remote_gdb.cc | 12 | ||||
| -rw-r--r-- | src/arch/mips/utility.cc | 4 |
4 files changed, 13 insertions, 13 deletions
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index f4f05ea48..59dba6870 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -139,12 +139,12 @@ output exec {{ //Read FCSR from FloatRegFile uint32_t fcsr_bits = - cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); + cpu->tcBase()->readFloatReg(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -157,13 +157,13 @@ output exec {{ fpResetCauseBits(ExecContext *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr); } }}; diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index 633199c94..46f81d597 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -286,7 +286,7 @@ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; typedef RegVal IntReg; // floating point register file entry type -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; // cop-0/cop-1 system control register typedef RegVal MiscReg; diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc index d490fa518..435bc0060 100644 --- a/src/arch/mips/remote_gdb.cc +++ b/src/arch/mips/remote_gdb.cc @@ -180,9 +180,9 @@ RemoteGDB::MipsGdbRegCache::getRegs(ThreadContext *context) r.badvaddr = context->readMiscRegNoEffect(MISCREG_BADVADDR); r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE); r.pc = context->pcState().pc(); - for (int i = 0; i < 32; i++) r.fpr[i] = context->readFloatRegBits(i); - r.fsr = context->readFloatRegBits(FLOATREG_FCCR); - r.fir = context->readFloatRegBits(FLOATREG_FIR); + for (int i = 0; i < 32; i++) r.fpr[i] = context->readFloatReg(i); + r.fsr = context->readFloatReg(FLOATREG_FCCR); + r.fir = context->readFloatReg(FLOATREG_FIR); } void @@ -197,9 +197,9 @@ RemoteGDB::MipsGdbRegCache::setRegs(ThreadContext *context) const context->setMiscRegNoEffect(MISCREG_BADVADDR, r.badvaddr); context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause); context->pcState(r.pc); - for (int i = 0; i < 32; i++) context->setFloatRegBits(i, r.fpr[i]); - context->setFloatRegBits(FLOATREG_FCCR, r.fsr); - context->setFloatRegBits(FLOATREG_FIR, r.fir); + for (int i = 0; i < 32; i++) context->setFloatReg(i, r.fpr[i]); + context->setFloatReg(FLOATREG_FCCR, r.fsr); + context->setFloatReg(FLOATREG_FIR, r.fir); } BaseGdbRegCache* diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index c8163b752..bb20c4cc9 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -225,7 +225,7 @@ zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatRegBits(ZeroReg, 0); + cpu->thread->setFloatReg(ZeroReg, 0); } void @@ -247,7 +247,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; i++) - dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); + dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); |