diff options
Diffstat (limited to 'src/arch/sparc')
23 files changed, 530 insertions, 1169 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 940cf2076..86ccaa010 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -34,11 +34,8 @@ Import('*') if env['TARGET_ISA'] == 'sparc': Source('asi.cc') Source('faults.cc') - Source('floatregfile.cc') - Source('intregfile.cc') - Source('miscregfile.cc') + Source('isa.cc') Source('pagetable.cc') - Source('regfile.cc') Source('remote_gdb.cc') Source('tlb.cc') Source('utility.cc') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc deleted file mode 100644 index 2d1af2218..000000000 --- a/src/arch/sparc/floatregfile.cc +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/floatregfile.hh" -#include "base/trace.hh" -#include "sim/byteswap.hh" -#include "sim/serialize.hh" - -#include <string.h> - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -void FloatRegFile::clear() -{ - memset(regSpace, 0, sizeof(regSpace)); -} - -FloatReg FloatRegFile::readReg(int floatReg, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatReg result; - switch(width) - { - case SingleWidth: - uint32_t result32; - float32_t fresult32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result32 = htog(result32); - memcpy(&fresult32, &result32, sizeof(result32)); - result = fresult32; - DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n", - floatReg, result, result32); - break; - case DoubleWidth: - uint64_t result64; - float64_t fresult64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result64 = htog(result64); - memcpy(&fresult64, &result64, sizeof(result64)); - result = fresult64; - DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n", - floatReg, result, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; -} - -FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatRegBits result; - switch(width) - { - case SingleWidth: - uint32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result = htog(result32); - DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n", - floatReg, result); - break; - case DoubleWidth: - uint64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result = htog(result64); - DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n", - floatReg, result); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; -} - -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - - uint32_t result32; - uint64_t result64; - float32_t fresult32; - float64_t fresult64; - switch(width) - { - case SingleWidth: - fresult32 = val; - memcpy(&result32, &fresult32, sizeof(result32)); - result32 = gtoh(result32); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - fresult64 = val; - memcpy(&result64, &fresult64, sizeof(result64)); - result64 = gtoh(result64); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return NoFault; -} - -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - uint32_t result32; - uint64_t result64; - switch(width) - { - case SingleWidth: - result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return NoFault; -} - -void FloatRegFile::serialize(std::ostream &os) -{ - uint8_t *float_reg = (uint8_t*)regSpace; - SERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); -} - -void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - uint8_t *float_reg = (uint8_t*)regSpace; - UNSERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); -} - diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/floatregfile.hh deleted file mode 100644 index 265e71b4a..000000000 --- a/src/arch/sparc/floatregfile.hh +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_FLOATREGFILE_HH__ -#define __ARCH_SPARC_FLOATREGFILE_HH__ - -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" - -#include <string> - -class Checkpoint; - -namespace SparcISA -{ - const int NumFloatArchRegs = 64; - const int NumFloatRegs = 64; - - typedef float float32_t; - typedef double float64_t; - //FIXME long double refers to a 10 byte float, rather than a - //16 byte float as required. This data type may have to be emulated. - typedef double float128_t; - - class FloatRegFile - { - public: - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; - - protected: - - //Since the floating point registers overlap each other, - //A generic storage space is used. The float to be returned is - //pulled from the appropriate section of this region. - char regSpace[(SingleWidth / 8) * NumFloatRegs]; - - public: - - void clear(); - - FloatReg readReg(int floatReg, int width); - - FloatRegBits readRegBits(int floatReg, int width); - - Fault setReg(int floatReg, const FloatReg &val, int width); - - Fault setRegBits(int floatReg, const FloatRegBits &val, int width); - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - }; -} - -#endif diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index ec930e2b0..353521a39 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -34,6 +34,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "cpu/thread_context.hh" #include "params/SparcInterrupts.hh" #include "sim/sim_object.hh" diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc deleted file mode 100644 index 54c30d1cc..000000000 --- a/src/arch/sparc/intregfile.cc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/intregfile.hh" -#include "base/trace.hh" -#include "base/misc.hh" -#include "sim/serialize.hh" - -#include <string.h> - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -void IntRegFile::clear() -{ - memset(regs, 0, sizeof(IntReg) * NumIntRegs); -} - -IntRegFile::IntRegFile() -{ - clear(); -} - -IntReg IntRegFile::readReg(int intReg) -{ - DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]); - return regs[intReg]; -} - -void IntRegFile::setReg(int intReg, const IntReg &val) -{ - if(intReg) - { - DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val); - regs[intReg] = val; - } - return; -} - -void IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); - SERIALIZE_ARRAY(microRegs, NumMicroIntRegs); -} - -void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); - UNSERIALIZE_ARRAY(microRegs, NumMicroIntRegs); -} diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/isa.cc index 38eba3862..3226b4e42 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,29 +26,65 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black - * Ali Saidi */ #include "arch/sparc/asi.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/isa.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -using namespace SparcISA; -using namespace std; - -class Checkpoint; +namespace SparcISA +{ enum RegMask { PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) }; -void MiscRegFile::clear() +void +ISA::reloadRegMap() +{ + installGlobals(gl, CurrentGlobalsOffset); + installWindow(cwp, CurrentWindowOffset); + // Microcode registers. + for (int i = 0; i < NumMicroIntRegs; i++) + intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16; + installGlobals(gl, NextGlobalsOffset); + installWindow(cwp - 1, NextWindowOffset); + installGlobals(gl, PreviousGlobalsOffset); + installWindow(cwp + 1, PreviousWindowOffset); +} + +void +ISA::installWindow(int cwp, int offset) { + assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs); + RegIndex *mapChunk = intRegMap + offset; + for (int i = 0; i < NumWindowedRegs; i++) + mapChunk[i] = TotalGlobals + + ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed)); +} + +void +ISA::installGlobals(int gl, int offset) +{ + assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs); + RegIndex *mapChunk = intRegMap + offset; + mapChunk[0] = 0; + for (int i = 1; i < NumGlobalRegs; i++) + mapChunk[i] = i + gl * NumGlobalRegs; +} + +void +ISA::clear() +{ + cwp = 0; + gl = 0; + reloadRegMap(); + //y = 0; //ccr = 0; asi = 0; @@ -66,13 +102,11 @@ void MiscRegFile::clear() pstate = 0; tl = 0; pil = 0; - cwp = 0; //cansave = 0; //canrestore = 0; //cleanwin = 0; //otherwin = 0; //wstate = 0; - gl = 0; //In a T1, bit 11 is apparently always 1 hpstate = (1 << 11); memset(htstate, 0, sizeof(htstate)); @@ -96,7 +130,8 @@ void MiscRegFile::clear() #endif } -MiscReg MiscRegFile::readRegNoEffect(int miscReg) +MiscReg +ISA::readMiscRegNoEffect(int miscReg) { // The three miscRegs are moved up from the switch statement @@ -255,7 +290,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) } } -MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) +MiscReg +ISA::readMiscReg(int miscReg, ThreadContext * tc) { switch (miscReg) { // tick and stick are aliased to each other in niagra @@ -311,10 +347,11 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) #endif } - return readRegNoEffect(miscReg); + return readMiscRegNoEffect(miscReg); } -void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) +void +ISA::setMiscRegNoEffect(int miscReg, MiscReg val) { switch (miscReg) { // case MISCREG_Y: @@ -493,8 +530,8 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) } } -void MiscRegFile::setReg(int miscReg, - const MiscReg &val, ThreadContext * tc) +void +ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) { MiscReg new_val = val; @@ -529,8 +566,15 @@ void MiscRegFile::setReg(int miscReg, new_val = val >= NWindows ? NWindows - 1 : val; if (val >= NWindows) new_val = NWindows - 1; + + installWindow(new_val, CurrentWindowOffset); + installWindow(new_val - 1, NextWindowOffset); + installWindow(new_val + 1, PreviousWindowOffset); break; case MISCREG_GL: + installGlobals(val, CurrentGlobalsOffset); + installGlobals(val, NextGlobalsOffset); + installGlobals(val, PreviousGlobalsOffset); break; case MISCREG_PIL: case MISCREG_SOFTINT: @@ -565,11 +609,11 @@ void MiscRegFile::setReg(int miscReg, miscReg, val); #endif } - setRegNoEffect(miscReg, new_val); + setMiscRegNoEffect(miscReg, new_val); } void -MiscRegFile::serialize(EventManager *em, std::ostream &os) +ISA::serialize(EventManager *em, std::ostream &os) { SERIALIZE_SCALAR(asi); SERIALIZE_SCALAR(tick); @@ -647,8 +691,7 @@ MiscRegFile::serialize(EventManager *em, std::ostream &os) } void -MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, - const string §ion) +ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) { UNSERIALIZE_SCALAR(asi); UNSERIALIZE_SCALAR(tick); @@ -668,6 +711,7 @@ MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, UNSERIALIZE_SCALAR(pil); UNSERIALIZE_SCALAR(cwp); UNSERIALIZE_SCALAR(gl); + reloadRegMap(); UNSERIALIZE_SCALAR(hpstate); UNSERIALIZE_ARRAY(htstate,MaxTL); UNSERIALIZE_SCALAR(hintp); @@ -722,3 +766,5 @@ MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, #endif } + +} diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/isa.hh index 9eff7fcac..9b4fd50d0 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,144 +26,26 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black - * Ali Saidi */ -#ifndef __ARCH_SPARC_MISCREGFILE_HH__ -#define __ARCH_SPARC_MISCREGFILE_HH__ +#ifndef __ARCH_SPARC_ISA_HH__ +#define __ARCH_SPARC_ISA_HH__ -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" +#include "config/full_system.hh" #include "cpu/cpuevent.hh" #include <string> +#include <ostream> class Checkpoint; +class EventManager; +class ThreadContext; namespace SparcISA { - enum MiscRegIndex - { - /** Ancillary State Registers */ -// MISCREG_Y, -// MISCREG_CCR, - MISCREG_ASI, - MISCREG_TICK, - MISCREG_FPRS, - MISCREG_PCR, - MISCREG_PIC, - MISCREG_GSR, - MISCREG_SOFTINT_SET, - MISCREG_SOFTINT_CLR, - MISCREG_SOFTINT, /* 10 */ - MISCREG_TICK_CMPR, - MISCREG_STICK, - MISCREG_STICK_CMPR, - - /** Privilged Registers */ - MISCREG_TPC, - MISCREG_TNPC, - MISCREG_TSTATE, - MISCREG_TT, - MISCREG_PRIVTICK, - MISCREG_TBA, - MISCREG_PSTATE, /* 20 */ - MISCREG_TL, - MISCREG_PIL, - MISCREG_CWP, -// MISCREG_CANSAVE, -// MISCREG_CANRESTORE, -// MISCREG_CLEANWIN, -// MISCREG_OTHERWIN, -// MISCREG_WSTATE, - MISCREG_GL, - - /** Hyper privileged registers */ - MISCREG_HPSTATE, /* 30 */ - MISCREG_HTSTATE, - MISCREG_HINTP, - MISCREG_HTBA, - MISCREG_HVER, - MISCREG_STRAND_STS_REG, - MISCREG_HSTICK_CMPR, - - /** Floating Point Status Register */ - MISCREG_FSR, - - /** MMU Internal Registers */ - MISCREG_MMU_P_CONTEXT, - MISCREG_MMU_S_CONTEXT, /* 40 */ - MISCREG_MMU_PART_ID, - MISCREG_MMU_LSU_CTRL, - - /** Scratchpad regiscers **/ - MISCREG_SCRATCHPAD_R0, /* 60 */ - MISCREG_SCRATCHPAD_R1, - MISCREG_SCRATCHPAD_R2, - MISCREG_SCRATCHPAD_R3, - MISCREG_SCRATCHPAD_R4, - MISCREG_SCRATCHPAD_R5, - MISCREG_SCRATCHPAD_R6, - MISCREG_SCRATCHPAD_R7, - - /* CPU Queue Registers */ - MISCREG_QUEUE_CPU_MONDO_HEAD, - MISCREG_QUEUE_CPU_MONDO_TAIL, - MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ - MISCREG_QUEUE_DEV_MONDO_TAIL, - MISCREG_QUEUE_RES_ERROR_HEAD, - MISCREG_QUEUE_RES_ERROR_TAIL, - MISCREG_QUEUE_NRES_ERROR_HEAD, - MISCREG_QUEUE_NRES_ERROR_TAIL, - - /* All the data for the TLB packed up in one register. */ - MISCREG_TLB_DATA, - MISCREG_NUMMISCREGS - }; - - struct HPSTATE { - const static uint64_t id = 0x800; // this impl. dependent (id) field m - const static uint64_t ibe = 0x400; - const static uint64_t red = 0x20; - const static uint64_t hpriv = 0x4; - const static uint64_t tlz = 0x1; - }; - - - struct PSTATE { - const static int cle = 0x200; - const static int tle = 0x100; - const static int mm = 0xC0; - const static int pef = 0x10; - const static int am = 0x8; - const static int priv = 0x4; - const static int ie = 0x2; - }; - - struct STS { - const static int st_idle = 0x00; - const static int st_wait = 0x01; - const static int st_halt = 0x02; - const static int st_run = 0x05; - const static int st_spec_run = 0x07; - const static int st_spec_rdy = 0x13; - const static int st_ready = 0x19; - const static int active = 0x01; - const static int speculative = 0x04; - const static int shft_id = 8; - const static int shft_fsm0 = 31; - const static int shft_fsm1 = 26; - const static int shft_fsm2 = 21; - const static int shft_fsm3 = 16; - }; - - - const int NumMiscArchRegs = MISCREG_NUMMISCREGS; - const int NumMiscRegs = MISCREG_NUMMISCREGS; - - // The control registers, broken out into fields - class MiscRegFile + class ISA { private: @@ -245,58 +127,86 @@ namespace SparcISA void processSTickCompare(ThreadContext *tc); void processHSTickCompare(ThreadContext *tc); - typedef CpuEventWrapper<MiscRegFile, - &MiscRegFile::processTickCompare> TickCompareEvent; + typedef CpuEventWrapper<ISA, + &ISA::processTickCompare> TickCompareEvent; TickCompareEvent *tickCompare; - typedef CpuEventWrapper<MiscRegFile, - &MiscRegFile::processSTickCompare> STickCompareEvent; + typedef CpuEventWrapper<ISA, + &ISA::processSTickCompare> STickCompareEvent; STickCompareEvent *sTickCompare; - typedef CpuEventWrapper<MiscRegFile, - &MiscRegFile::processHSTickCompare> HSTickCompareEvent; + typedef CpuEventWrapper<ISA, + &ISA::processHSTickCompare> HSTickCompareEvent; HSTickCompareEvent *hSTickCompare; #endif + + static const int NumGlobalRegs = 8; + static const int NumWindowedRegs = 24; + static const int WindowOverlap = 8; + + static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs; + static const int RegsPerWindow = NumWindowedRegs - WindowOverlap; + static const int TotalWindowed = NWindows * RegsPerWindow; + + enum InstIntRegOffsets { + CurrentGlobalsOffset = 0, + CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs, + MicroIntOffset = CurrentWindowOffset + NumWindowedRegs, + NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs, + NextWindowOffset = NextGlobalsOffset + NumGlobalRegs, + PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs, + PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs, + TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs + }; + + RegIndex intRegMap[TotalInstIntRegs]; + void installWindow(int cwp, int offset); + void installGlobals(int gl, int offset); + void reloadRegMap(); + public: void clear(); - MiscRegFile() - { - clear(); - } + void serialize(EventManager *em, std::ostream & os); - MiscReg readRegNoEffect(int miscReg); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string & section); - MiscReg readReg(int miscReg, ThreadContext *tc); + protected: + + bool isHyperPriv() { return (hpstate & (1 << 2)); } + bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } + bool isNonPriv() { return !isPriv(); } - void setRegNoEffect(int miscReg, const MiscReg &val); + public: - void setReg(int miscReg, - const MiscReg &val, ThreadContext * tc); + MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); - int getInstAsid() + void setMiscRegNoEffect(int miscReg, const MiscReg val); + void setMiscReg(int miscReg, const MiscReg val, + ThreadContext *tc); + + int + flattenIntIndex(int reg) { - return priContext | (uint32_t)partId << 13; + assert(reg < TotalInstIntRegs); + RegIndex flatIndex = intRegMap[reg]; + assert(flatIndex < NumIntRegs); + return flatIndex; } - int getDataAsid() + int + flattenFloatIndex(int reg) { - return priContext | (uint32_t)partId << 13; + return reg; } - void serialize(EventManager *em, std::ostream & os); - - void unserialize(EventManager *em, Checkpoint *cp, - const std::string & section); - - void copyMiscRegs(ThreadContext * tc); - - protected: - - bool isHyperPriv() { return (hpstate & (1 << 2)); } - bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } - bool isNonPriv() { return !isPriv(); } + ISA() + { + clear(); + } }; } diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 135bd58c3..bc9273ad3 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -40,7 +40,7 @@ output header {{ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/condcodes.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 00dadcf3d..2af624d39 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -33,7 +33,6 @@ #define __ARCH_SPARC_ISA_TRAITS_HH__ #include "arch/sparc/types.hh" -#include "arch/sparc/max_inst_regs.hh" #include "arch/sparc/sparc_traits.hh" #include "base/types.hh" #include "config/full_system.hh" @@ -44,14 +43,10 @@ namespace BigEndianGuest {} namespace SparcISA { - class RegFile; - const int MachineBytes = 8; //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; - using SparcISAInst::MaxInstSrcRegs; - using SparcISAInst::MaxInstDestRegs; // SPARC has a delay slot #define ISA_HAS_DELAY_SLOT 1 @@ -59,23 +54,6 @@ namespace SparcISA // SPARC NOP (sethi %(hi(0), g0) const MachInst NoopMachInst = 0x01000000; - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - FP_Base_DepTag = 32*3+9, - Ctrl_Base_DepTag = FP_Base_DepTag + 64 - }; - - // semantically meaningful register indices - const int ZeroReg = 0; // architecturally meaningful - // the rest of these depend on the ABI - const int ReturnAddressReg = 31; // post call, precall is 15 - const int ReturnValueReg = 8; // Post return, 24 is pre-return. - const int StackPointerReg = 14; - const int FramePointerReg = 30; - - // Some OS syscall use a second register (o1) to return a second value - const int SyscallPseudoReturnReg = 9; - //8K. This value is implmentation specific; and should probably //be somewhere else. const int LogVMPageSize = 13; diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index 28aa1e50c..b39508386 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -32,7 +32,7 @@ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/linux/process.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh new file mode 100644 index 000000000..f7fff6ee0 --- /dev/null +++ b/src/arch/sparc/miscregs.hh @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +#ifndef __ARCH_SPARC_MISCREGS_HH__ +#define __ARCH_SPARC_MISCREGS_HH__ + +#include "base/types.hh" + +namespace SparcISA +{ + enum MiscRegIndex + { + /** Ancillary State Registers */ +// MISCREG_Y, +// MISCREG_CCR, + MISCREG_ASI, + MISCREG_TICK, + MISCREG_FPRS, + MISCREG_PCR, + MISCREG_PIC, + MISCREG_GSR, + MISCREG_SOFTINT_SET, + MISCREG_SOFTINT_CLR, + MISCREG_SOFTINT, /* 10 */ + MISCREG_TICK_CMPR, + MISCREG_STICK, + MISCREG_STICK_CMPR, + + /** Privilged Registers */ + MISCREG_TPC, + MISCREG_TNPC, + MISCREG_TSTATE, + MISCREG_TT, + MISCREG_PRIVTICK, + MISCREG_TBA, + MISCREG_PSTATE, /* 20 */ + MISCREG_TL, + MISCREG_PIL, + MISCREG_CWP, +// MISCREG_CANSAVE, +// MISCREG_CANRESTORE, +// MISCREG_CLEANWIN, +// MISCREG_OTHERWIN, +// MISCREG_WSTATE, + MISCREG_GL, + + /** Hyper privileged registers */ + MISCREG_HPSTATE, /* 30 */ + MISCREG_HTSTATE, + MISCREG_HINTP, + MISCREG_HTBA, + MISCREG_HVER, + MISCREG_STRAND_STS_REG, + MISCREG_HSTICK_CMPR, + + /** Floating Point Status Register */ + MISCREG_FSR, + + /** MMU Internal Registers */ + MISCREG_MMU_P_CONTEXT, + MISCREG_MMU_S_CONTEXT, /* 40 */ + MISCREG_MMU_PART_ID, + MISCREG_MMU_LSU_CTRL, + + /** Scratchpad regiscers **/ + MISCREG_SCRATCHPAD_R0, /* 60 */ + MISCREG_SCRATCHPAD_R1, + MISCREG_SCRATCHPAD_R2, + MISCREG_SCRATCHPAD_R3, + MISCREG_SCRATCHPAD_R4, + MISCREG_SCRATCHPAD_R5, + MISCREG_SCRATCHPAD_R6, + MISCREG_SCRATCHPAD_R7, + + /* CPU Queue Registers */ + MISCREG_QUEUE_CPU_MONDO_HEAD, + MISCREG_QUEUE_CPU_MONDO_TAIL, + MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ + MISCREG_QUEUE_DEV_MONDO_TAIL, + MISCREG_QUEUE_RES_ERROR_HEAD, + MISCREG_QUEUE_RES_ERROR_TAIL, + MISCREG_QUEUE_NRES_ERROR_HEAD, + MISCREG_QUEUE_NRES_ERROR_TAIL, + + /* All the data for the TLB packed up in one register. */ + MISCREG_TLB_DATA, + MISCREG_NUMMISCREGS + }; + + struct HPSTATE { + const static uint64_t id = 0x800; // this impl. dependent (id) field m + const static uint64_t ibe = 0x400; + const static uint64_t red = 0x20; + const static uint64_t hpriv = 0x4; + const static uint64_t tlz = 0x1; + }; + + + struct PSTATE { + const static int cle = 0x200; + const static int tle = 0x100; + const static int mm = 0xC0; + const static int pef = 0x10; + const static int am = 0x8; + const static int priv = 0x4; + const static int ie = 0x2; + }; + + struct STS { + const static int st_idle = 0x00; + const static int st_wait = 0x01; + const static int st_halt = 0x02; + const static int st_run = 0x05; + const static int st_spec_run = 0x07; + const static int st_spec_rdy = 0x13; + const static int st_ready = 0x19; + const static int active = 0x01; + const static int speculative = 0x04; + const static int shft_id = 8; + const static int shft_fsm0 = 31; + const static int shft_fsm1 = 26; + const static int shft_fsm2 = 21; + const static int shft_fsm3 = 16; + }; + + + const int NumMiscArchRegs = MISCREG_NUMMISCREGS; + const int NumMiscRegs = MISCREG_NUMMISCREGS; +} + +#endif diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 7775e858e..c4ab4fe79 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -31,7 +31,9 @@ #ifndef __ARCH_SPARC_PREDECODER_HH__ #define __ARCH_SPARC_PREDECODER_HH__ +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" +#include "base/bitfield.hh" #include "base/misc.hh" #include "base/types.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 533e385b3..89e853573 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -32,6 +32,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/handlers.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/process.hh" #include "arch/sparc/types.hh" #include "base/loader/object_file.hh" @@ -139,7 +140,7 @@ SparcLiveProcess::startup() //tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); tc->setIntReg(NumIntArchRegs + 5, NWindows); //Start with register window 0 - tc->setMiscRegNoEffect(MISCREG_CWP, 0); + tc->setMiscReg(MISCREG_CWP, 0); //Always use spill and fill traps 0 //tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); tc->setIntReg(NumIntArchRegs + 7, 0); diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc deleted file mode 100644 index a88c6c931..000000000 --- a/src/arch/sparc/regfile.cc +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/regfile.hh" -#include "cpu/thread_context.hh" - -class Checkpoint; - -using namespace SparcISA; -using namespace std; - -//RegFile class methods -Addr RegFile::readPC() -{ - return pc; -} - -void RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr RegFile::readNextPC() -{ - return npc; -} - -void RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr RegFile::readNextNPC() -{ - return nnpc; -} - -void RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void RegFile::clear() -{ - floatRegFile.clear(); - intRegFile.clear(); - miscRegFile.clear(); -} - -MiscReg RegFile::readMiscRegNoEffect(int miscReg) -{ - return miscRegFile.readRegNoEffect(miscReg); -} - -MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) -{ - return miscRegFile.readReg(miscReg, tc); -} - -void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) -{ - miscRegFile.setRegNoEffect(miscReg, val); -} - -void RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) -{ - miscRegFile.setReg(miscReg, val, tc); -} - -FloatReg RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg, width); -} - -FloatReg RegFile::readFloatReg(int floatReg) -{ - //Use the "natural" width of a single float - return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg, width); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg) -{ - //Use the "natural" width of a single float - return floatRegFile.readRegBits(floatReg, - FloatRegFile::SingleWidth); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) -{ - floatRegFile.setReg(floatReg, val, width); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val) -{ - //Use the "natural" width of a single float - setFloatReg(floatReg, val, FloatRegFile::SingleWidth); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - floatRegFile.setRegBits(floatReg, val, width); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - //Use the "natural" width of a single float - floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); -} - -IntReg RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -void RegFile::setIntReg(int intReg, const IntReg &val) -{ - intRegFile.setReg(intReg, val); -} - -int SparcISA::flattenIntIndex(ThreadContext * tc, int reg) -{ - int gl = tc->readMiscRegNoEffect(MISCREG_GL); - int cwp = tc->readMiscRegNoEffect(MISCREG_CWP); - //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); - int newReg; - //The total number of global registers - int numGlobals = (MaxGL + 1) * 8; - if(reg < 8) - { - //Global register - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else if(reg < NumIntArchRegs) - { - //Regular windowed register - //Put it in the window pointed to by cwp - newReg = numGlobals + - ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); - } - else if(reg < NumIntArchRegs + NumMicroIntRegs) - { - //Microcode register - //Displace from the end of the regular registers - newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; - } - else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the next window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the previous window - //Put it in the window before the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (2 * NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the previous window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the next window - //Put it in the window after the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else - panic("Tried to flatten invalid register index %d!\n", reg); - DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); - return newReg; - //return intRegFile.flattenIndex(reg); -} - -void -RegFile::serialize(EventManager *em, ostream &os) -{ - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(em, os); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(em, cp, section); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); -} - -void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - - uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); - - // Read all the trap level dependent registers and save them off - for(int i = 1; i <= MaxTL; i++) - { - src->setMiscRegNoEffect(MISCREG_TL, i); - dest->setMiscRegNoEffect(MISCREG_TL, i); - - dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); - dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); - dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); - dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); - } - - // Save off the traplevel - dest->setMiscRegNoEffect(MISCREG_TL, tl); - src->setMiscRegNoEffect(MISCREG_TL, tl); - - - // ASRs -// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); -// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); - dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); - dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); - dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); - dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); - dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); - dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); - dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); - - // Priv Registers - dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); - dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); - dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); - dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); - dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); -// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); -// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); -// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); -// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); -// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); - dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); - - // Hyperprivilged registers - dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); - dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); - dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); - dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, - src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); - dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, - src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); - - // FSR - dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); - - //Strand Status Register - dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, - src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); - - // MMU Registers - dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, - src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); - dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, - src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); - dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, - src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); - dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, - src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); - - // Scratchpad Registers - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); - - // Queue Registers - dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); -} - -void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - //First loop through the integer registers. - int old_gl = src->readMiscRegNoEffect(MISCREG_GL); - int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); - //Globals - for (int x = 0; x < MaxGL; ++x) { - src->setMiscRegNoEffect(MISCREG_GL, x); - dest->setMiscRegNoEffect(MISCREG_GL, x); - // Skip %g0 which is always zero. - for (int y = 1; y < 8; y++) - dest->setIntReg(y, src->readIntReg(y)); - } - //Locals and ins. Outs are all also ins. - for (int x = 0; x < NWindows; ++x) { - src->setMiscRegNoEffect(MISCREG_CWP, x); - dest->setMiscRegNoEffect(MISCREG_CWP, x); - for (int y = 16; y < 32; y++) - dest->setIntReg(y, src->readIntReg(y)); - } - //Microcode reg and pseudo int regs (misc regs in the integer regfile). - for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) - dest->setIntReg(y, src->readIntReg(y)); - - //Restore src's GL, CWP - src->setMiscRegNoEffect(MISCREG_GL, old_gl); - src->setMiscRegNoEffect(MISCREG_CWP, old_cwp); - - - // Then loop through the floating point registers. - for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { - dest->setFloatRegBits(i, src->readFloatRegBits(i)); - } - - // Copy misc. registers - copyMiscRegs(src, dest); - - - // Lastly copy PC/NPC - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); - dest->setNextNPC(src->readNextNPC()); -} - diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh deleted file mode 100644 index 7da302eb7..000000000 --- a/src/arch/sparc/regfile.hh +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_REGFILE_HH__ -#define __ARCH_SPARC_REGFILE_HH__ - -#include <string> - -#include "arch/sparc/floatregfile.hh" -#include "arch/sparc/intregfile.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregfile.hh" -#include "arch/sparc/types.hh" -#include "base/types.hh" - -class Checkpoint; - -namespace SparcISA -{ - class RegFile - { - protected: - Addr pc; // Program Counter - Addr npc; // Next Program Counter - Addr nnpc; - - public: - Addr readPC(); - void setPC(Addr val); - - Addr readNextPC(); - void setNextPC(Addr val); - - Addr readNextNPC(); - void setNextNPC(Addr val); - - protected: - IntRegFile intRegFile; // integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: - - void clear(); - - MiscReg readMiscRegNoEffect(int miscReg); - - MiscReg readMiscReg(int miscReg, ThreadContext *tc); - - void setMiscRegNoEffect(int miscReg, const MiscReg &val); - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc); - - int instAsid() - { - return miscRegFile.getInstAsid(); - } - - int dataAsid() - { - return miscRegFile.getDataAsid(); - } - - FloatReg readFloatReg(int floatReg, int width); - - FloatReg readFloatReg(int floatReg); - - FloatRegBits readFloatRegBits(int floatReg, int width); - - FloatRegBits readFloatRegBits(int floatReg); - - void setFloatReg(int floatReg, const FloatReg &val, int width); - - void setFloatReg(int floatReg, const FloatReg &val); - - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - - void setFloatRegBits(int floatReg, const FloatRegBits &val); - - IntReg readIntReg(int intReg); - - void setIntReg(int intReg, const IntReg &val); - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - public: - }; - - int flattenIntIndex(ThreadContext * tc, int reg); - - static inline int - flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -} // namespace SparcISA - -#endif diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/registers.hh index f669f6b0d..639b7a487 100644 --- a/src/arch/sparc/intregfile.hh +++ b/src/arch/sparc/registers.hh @@ -29,42 +29,52 @@ * Ali Saidi */ -#ifndef __ARCH_SPARC_INTREGFILE_HH__ -#define __ARCH_SPARC_INTREGFILE_HH__ +#ifndef __ARCH_SPARC_REGISTERS_HH__ +#define __ARCH_SPARC_REGISTERS_HH__ -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" -#include "base/bitfield.hh" - -#include <string> - -class Checkpoint; +#include "arch/sparc/max_inst_regs.hh" +#include "arch/sparc/miscregs.hh" +#include "arch/sparc/sparc_traits.hh" +#include "base/types.hh" namespace SparcISA { - const int NumIntArchRegs = 32; - const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; + using SparcISAInst::MaxInstSrcRegs; + using SparcISAInst::MaxInstDestRegs; - class IntRegFile + typedef uint64_t IntReg; + typedef uint64_t MiscReg; + typedef float FloatReg; + typedef uint32_t FloatRegBits; + typedef union { - protected: - IntReg microRegs[NumMicroIntRegs]; - IntReg regs[NumIntRegs]; - - public: + IntReg intReg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; - void clear(); + typedef uint16_t RegIndex; - IntRegFile(); + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + FP_Base_DepTag = 32*3+9, + Ctrl_Base_DepTag = FP_Base_DepTag + 64 + }; - IntReg readReg(int intReg); + // semantically meaningful register indices + const int ZeroReg = 0; // architecturally meaningful + // the rest of these depend on the ABI + const int ReturnAddressReg = 31; // post call, precall is 15 + const int ReturnValueReg = 8; // Post return, 24 is pre-return. + const int StackPointerReg = 14; + const int FramePointerReg = 30; - void setReg(int intReg, const IntReg &val); + // Some OS syscall use a second register (o1) to return a second value + const int SyscallPseudoReturnReg = 9; - void serialize(std::ostream &os); + const int NumIntArchRegs = 32; + const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - void unserialize(Checkpoint *cp, const std::string §ion); - }; -} +} // namespace SparcISA #endif diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index 22924736b..eafb488df 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -30,7 +30,7 @@ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/solaris/process.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh index e154ba274..b8e3c2aef 100644 --- a/src/arch/sparc/sparc_traits.hh +++ b/src/arch/sparc/sparc_traits.hh @@ -49,7 +49,8 @@ namespace SparcISA // const int NumIntRegs = // NumRegularIntRegs + // NumMicroIntRegs; -// const int NumFloatRegs = 64; + const int NumFloatRegs = 64; + const int NumFloatArchRegs = NumFloatRegs; // const int NumMiscRegs = 40; } diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 64d73c3c1..1b84a0784 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -31,7 +31,7 @@ #include <cstring> #include "arch/sparc/asi.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/tlb.hh" #include "base/bitfield.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index 501e2e8cb..70558ec6d 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -39,19 +39,7 @@ namespace SparcISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - typedef uint64_t IntReg; typedef Twin64_t LargestRead; - typedef uint64_t MiscReg; - typedef double FloatReg; - typedef uint64_t FloatRegBits; - typedef union - { - IntReg intReg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - typedef uint16_t RegIndex; struct CoreSpecific { int core_type; diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index d126d5944..95381db38 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -26,8 +26,9 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/sparc/isa.hh" #include "arch/sparc/kernel_stats.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" @@ -39,7 +40,7 @@ using namespace std; void -MiscRegFile::checkSoftInt(ThreadContext *tc) +ISA::checkSoftInt(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -84,7 +85,7 @@ getMiscRegName(RegIndex index) } void -MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) +ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -92,18 +93,18 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - setRegNoEffect(miscReg, val);; + setMiscRegNoEffect(miscReg, val);; checkSoftInt(tc); break; case MISCREG_SOFTINT_CLR: - return setReg(MISCREG_SOFTINT, ~val & softint, tc); + return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); case MISCREG_SOFTINT_SET: - return setReg(MISCREG_SOFTINT, val | softint, tc); + return setMiscReg(MISCREG_SOFTINT, val | softint, tc); case MISCREG_TICK_CMPR: if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) cpu->deschedule(tickCompare); time = (tick_cmpr & mask(63)) - (tick & mask(63)); @@ -118,7 +119,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) cpu->deschedule(sTickCompare); time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - @@ -132,10 +133,10 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_PSTATE: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); case MISCREG_PIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); checkSoftInt(tc); break; @@ -143,7 +144,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) panic("Shouldn't be writing HVER\n"); case MISCREG_HINTP: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (hintp) cpu->postInterrupt(IT_HINTP, 0); else @@ -152,12 +153,12 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HTBA: // clear lower 7 bits on writes. - setRegNoEffect(miscReg, val & ULL(~0x7FFF)); + setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); break; case MISCREG_QUEUE_CPU_MONDO_HEAD: case MISCREG_QUEUE_CPU_MONDO_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (cpu_mondo_head != cpu_mondo_tail) cpu->postInterrupt(IT_CPU_MONDO, 0); else @@ -165,7 +166,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_DEV_MONDO_HEAD: case MISCREG_QUEUE_DEV_MONDO_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (dev_mondo_head != dev_mondo_tail) cpu->postInterrupt(IT_DEV_MONDO, 0); else @@ -173,7 +174,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_RES_ERROR_HEAD: case MISCREG_QUEUE_RES_ERROR_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (res_error_head != res_error_tail) cpu->postInterrupt(IT_RES_ERROR, 0); else @@ -181,14 +182,14 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); // This one doesn't have an interrupt to report to the guest OS break; case MISCREG_HSTICK_CMPR: if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) cpu->deschedule(hSTickCompare); time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - @@ -203,7 +204,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HPSTATE: // T1000 spec says impl. dependent val must always be 1 - setRegNoEffect(miscReg, val | HPSTATE::id); + setMiscRegNoEffect(miscReg, val | HPSTATE::id); #if FULL_SYSTEM if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); @@ -212,13 +213,13 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) #endif break; case MISCREG_HTSTATE: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); break; case MISCREG_STRAND_STS_REG: if (bits(val,2,2)) panic("No support for setting spec_en bit\n"); - setRegNoEffect(miscReg, bits(val,0,0)); + setMiscRegNoEffect(miscReg, bits(val,0,0)); if (!bits(val,0,0)) { DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep @@ -235,7 +236,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) } MiscReg -MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) +ISA::readFSReg(int miscReg, ThreadContext * tc) { uint64_t temp; @@ -257,10 +258,10 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) case MISCREG_HINTP: case MISCREG_HTSTATE: case MISCREG_HSTICK_CMPR: - return readRegNoEffect(miscReg) ; + return readMiscRegNoEffect(miscReg) ; case MISCREG_HTBA: - return readRegNoEffect(miscReg) & ULL(~0x7FFF); + return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: // XXX set to match Legion return ULL(0x3e) << 48 | @@ -275,7 +276,7 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) int x; sys = tc->getSystemPtr(); - temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); + temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); // Check that the CPU array is fully populated // (by calling getNumCPus()) assert(sys->numContexts() > tc->contextId()); @@ -309,13 +310,13 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) } void -MiscRegFile::processTickCompare(ThreadContext *tc) +ISA::processTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processSTickCompare(ThreadContext *tc) +ISA::processSTickCompare(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -331,14 +332,14 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { - setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); + setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); } void -MiscRegFile::processHSTickCompare(ThreadContext *tc) +ISA::processHSTickCompare(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -357,7 +358,7 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { - setReg(MISCREG_HINTP, 1, tc); + setMiscReg(MISCREG_HINTP, 1, tc); } // Need to do something to cause interrupt to happen here !!! @todo } else diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index d4cc286e6..84e700f6d 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -61,4 +61,159 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) { M5_DUMMY_RETURN #endif } + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + + uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); + + // Read all the trap level dependent registers and save them off + for(int i = 1; i <= MaxTL; i++) + { + src->setMiscRegNoEffect(MISCREG_TL, i); + dest->setMiscRegNoEffect(MISCREG_TL, i); + + dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); + dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); + dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); + dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); + } + + // Save off the traplevel + dest->setMiscRegNoEffect(MISCREG_TL, tl); + src->setMiscRegNoEffect(MISCREG_TL, tl); + + + // ASRs +// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); +// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); + dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); + dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); + dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); + dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); + dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); + + // Priv Registers + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); + dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); + dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); + dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); +// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); +// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); +// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); +// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); +// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); + dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); + + // Hyperprivilged registers + dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); + dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); + dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, + src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); + + // FSR + dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); + + //Strand Status Register + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + + // MMU Registers + dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, + src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); + dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, + src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); + + // Scratchpad Registers + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); + + // Queue Registers + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); +} + +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + //First loop through the integer registers. + int old_gl = src->readMiscRegNoEffect(MISCREG_GL); + int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); + //Globals + for (int x = 0; x < MaxGL; ++x) { + src->setMiscReg(MISCREG_GL, x); + dest->setMiscReg(MISCREG_GL, x); + // Skip %g0 which is always zero. + for (int y = 1; y < 8; y++) + dest->setIntReg(y, src->readIntReg(y)); + } + //Locals and ins. Outs are all also ins. + for (int x = 0; x < NWindows; ++x) { + src->setMiscReg(MISCREG_CWP, x); + dest->setMiscReg(MISCREG_CWP, x); + for (int y = 16; y < 32; y++) + dest->setIntReg(y, src->readIntReg(y)); + } + //Microcode reg and pseudo int regs (misc regs in the integer regfile). + for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) + dest->setIntReg(y, src->readIntReg(y)); + + //Restore src's GL, CWP + src->setMiscReg(MISCREG_GL, old_gl); + src->setMiscReg(MISCREG_CWP, old_cwp); + + + // Then loop through the floating point registers. + for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { + dest->setFloatRegBits(i, src->readFloatRegBits(i)); + } + + // Copy misc. registers + copyMiscRegs(src, dest); + + + // Lastly copy PC/NPC + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); + dest->setNextNPC(src->readNextNPC()); +} } //namespace SPARC_ISA diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 4ad8950b1..2b9059371 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -33,6 +33,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/tlb.hh" #include "base/misc.hh" #include "base/bitfield.hh" @@ -115,6 +116,10 @@ namespace SparcISA #endif } + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + } // namespace SparcISA #endif |