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-rw-r--r--src/arch/sparc/faults.cc15
-rw-r--r--src/arch/sparc/isa/decoder.isa6
-rw-r--r--src/arch/sparc/miscregfile.cc62
-rw-r--r--src/arch/sparc/miscregfile.hh16
-rw-r--r--src/arch/sparc/regfile.cc31
-rw-r--r--src/arch/sparc/regfile.hh28
-rw-r--r--src/arch/sparc/tlb.hh28
7 files changed, 121 insertions, 65 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 2c8da44c5..567ca5f5c 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -359,21 +359,6 @@ void SparcFault::invoke(ThreadContext * tc)
countStat()++;
//Use the SPARC trap state machine
- /*// exception restart address
- if (setRestartAddress() || !tc->inPalMode())
- tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
-
- if (skipFaultingInstruction()) {
- // traps... skip faulting instruction.
- tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
- tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
- }
-
- if (!tc->inPalMode())
- AlphaISA::swap_palshadow(&(tc->regs), true);
-
- tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
- tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
}
#endif
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index a64ff09bb..a5f43367d 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -353,14 +353,14 @@ decode OP default Unknown::unknown()
0x1: Nop::membar({{/*stuff*/}});
}
default: rdasr({{
- Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
+ Rd = xc->readMiscRegWithEffect(RS1 + AsrStart);
}});
}
0x29: HPriv::rdhpr({{
- Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
+ Rd = xc->readMiscRegWithEffect(RS1 + HprStart);
}});
0x2A: Priv::rdpr({{
- Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
+ Rd = xc->readMiscRegWithEffect(RS1 + PrStart);
}});
0x2B: BasicOperate::flushw({{
if(NWindows - 2 - Cansave == 0)
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index bf4572878..2f3cfb417 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -59,20 +59,21 @@ string SparcISA::getMiscRegName(RegIndex index)
//XXX These need an implementation someplace
/** Fullsystem only register version of ReadRegWithEffect() */
-MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext *tc);
/** Fullsystem only register version of SetRegWithEffect() */
-Fault MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
+void MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc);
#endif
void MiscRegFile::reset()
{
- pstateFields.pef = 0; //No FPU
+ //pstateFields.pef = 0; //No FPU
//pstateFields.pef = 1; //FPU
#if FULL_SYSTEM
//For SPARC, when a system is first started, there is a power
//on reset Trap which sets the processor into the following state.
//Bits that aren't set aren't defined on startup.
+ //XXX this code should be moved into the POR fault.
tl = MaxTL;
gl = MaxGL;
@@ -98,22 +99,6 @@ void MiscRegFile::reset()
hintp = 0; // no interrupts pending
hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-#else
-/* //This sets up the initial state of the processor for usermode processes
- pstateFields.priv = 0; //Process runs in user mode
- pstateFields.ie = 1; //Interrupts are enabled
- fsrFields.rd = 0; //Round to nearest
- fsrFields.tem = 0; //Floating point traps not enabled
- fsrFields.ns = 0; //Non standard mode off
- fsrFields.qne = 0; //Floating point queue is empty
- fsrFields.aexc = 0; //No accrued exceptions
- fsrFields.cexc = 0; //No current exceptions
-
- //Register window management registers
- otherwin = 0; //No windows contain info from other programs
- canrestore = 0; //There are no windows to pop
- cansave = MaxTL - 2; //All windows are available to save into
- cleanwin = MaxTL;*/
#endif
}
@@ -337,6 +322,30 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
}
}
+inline void MiscRegFile::setImplicitAsis()
+{
+ //The spec seems to use trap level to indicate the privilege level of the
+ //processor. It's unclear whether the implicit ASIs should directly depend
+ //on the trap level, or if they should really be based on the privelege
+ //bits
+ if(tl == 0)
+ {
+ implicitInstAsi = implicitDataAsi =
+ pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
+ }
+ else if(tl <= MaxPTL)
+ {
+ implicitInstAsi = ASI_NUCLEUS;
+ implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
+ }
+ else
+ {
+ //This is supposed to force physical addresses to match the spec.
+ //It might not because of context values and partition values.
+ implicitInstAsi = implicitDataAsi = ASI_REAL;
+ }
+}
+
void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
@@ -352,6 +361,14 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_PCR:
//Set up performance counting based on pcr value
break;
+ case MISCREG_PSTATE:
+ pstate = val;
+ setImplicitAsis();
+ return;
+ case MISCREG_TL:
+ tl = val;
+ setImplicitAsis();
+ return;
case MISCREG_CWP:
tc->changeRegFileContext(CONTEXT_CWP, val);
break;
@@ -389,6 +406,8 @@ void MiscRegFile::serialize(std::ostream & os)
SERIALIZE_ARRAY(htstate, MaxTL);
SERIALIZE_SCALAR(htba);
SERIALIZE_SCALAR(hstick_cmpr);
+ SERIALIZE_SCALAR((int)implicitInstAsi);
+ SERIALIZE_SCALAR((int)implicitDataAsi);
}
void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
@@ -418,5 +437,10 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
UNSERIALIZE_ARRAY(htstate, MaxTL);
UNSERIALIZE_SCALAR(htba);
UNSERIALIZE_SCALAR(hstick_cmpr);
+ int temp;
+ UNSERIALIZE_SCALAR(temp);
+ implicitInstAsi = (ASI)temp;
+ UNSERIALIZE_SCALAR(temp);
+ implicitDataAsi = (ASI)temp;
}
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 771cb1ed6..ac1ad90b9 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -32,9 +32,11 @@
#ifndef __ARCH_SPARC_MISCREGFILE_HH__
#define __ARCH_SPARC_MISCREGFILE_HH__
+#include "arch/sparc/asi.hh"
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/types.hh"
+#include "cpu/cpuevent.hh"
#include <string>
@@ -329,6 +331,9 @@ namespace SparcISA
} fsrFields;
};
+ ASI implicitInstAsi;
+ ASI implicitDataAsi;
+
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
#if FULL_SYSTEM
@@ -374,6 +379,16 @@ namespace SparcISA
void setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc);
+ ASI getInstAsid()
+ {
+ return implicitInstAsi;
+ }
+
+ ASI getDataAsid()
+ {
+ return implicitDataAsi;
+ }
+
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, const std::string & section);
@@ -385,6 +400,7 @@ namespace SparcISA
bool isHyperPriv() { return hpstateFields.hpriv; }
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
bool isNonPriv() { return !isPriv(); }
+ inline void setImplicitAsis();
};
}
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 5eb874d39..65e6017da 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -79,24 +79,20 @@ MiscReg RegFile::readMiscReg(int miscReg)
return miscRegFile.readReg(miscReg);
}
-MiscReg RegFile::readMiscRegWithEffect(int miscReg,
- Fault &fault, ThreadContext *tc)
+MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
{
- fault = NoFault;
return miscRegFile.readRegWithEffect(miscReg, tc);
}
-Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
+void RegFile::setMiscReg(int miscReg, const MiscReg &val)
{
miscRegFile.setReg(miscReg, val);
- return NoFault;
}
-Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc)
{
miscRegFile.setRegWithEffect(miscReg, val, tc);
- return NoFault;
}
FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -122,27 +118,26 @@ FloatRegBits RegFile::readFloatRegBits(int floatReg)
FloatRegFile::SingleWidth);
}
-Fault RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
+void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
{
- return floatRegFile.setReg(floatReg, val, width);
+ floatRegFile.setReg(floatReg, val, width);
}
-Fault RegFile::setFloatReg(int floatReg, const FloatReg &val)
+void RegFile::setFloatReg(int floatReg, const FloatReg &val)
{
//Use the "natural" width of a single float
- return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
+ setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
}
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
{
- return floatRegFile.setRegBits(floatReg, val, width);
+ floatRegFile.setRegBits(floatReg, val, width);
}
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
{
//Use the "natural" width of a single float
- return floatRegFile.setRegBits(floatReg, val,
- FloatRegFile::SingleWidth);
+ floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
}
IntReg RegFile::readIntReg(int intReg)
@@ -150,9 +145,9 @@ IntReg RegFile::readIntReg(int intReg)
return intRegFile.readReg(intReg);
}
-Fault RegFile::setIntReg(int intReg, const IntReg &val)
+void RegFile::setIntReg(int intReg, const IntReg &val)
{
- return intRegFile.setReg(intReg, val);
+ intRegFile.setReg(intReg, val);
}
void RegFile::serialize(std::ostream &os)
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 500fbbba4..9f33435f6 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -32,7 +32,6 @@
#ifndef __ARCH_SPARC_REGFILE_HH__
#define __ARCH_SPARC_REGFILE_HH__
-#include "arch/sparc/faults.hh"
#include "arch/sparc/floatregfile.hh"
#include "arch/sparc/intregfile.hh"
#include "arch/sparc/isa_traits.hh"
@@ -76,14 +75,23 @@ namespace SparcISA
MiscReg readMiscReg(int miscReg);
- MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ThreadContext *tc);
+ MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
- Fault setMiscReg(int miscReg, const MiscReg &val);
+ void setMiscReg(int miscReg, const MiscReg &val);
- Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ void setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc);
+ ASI instAsid()
+ {
+ return miscRegFile.getInstAsid();
+ }
+
+ ASI dataAsid()
+ {
+ return miscRegFile.getDataAsid();
+ }
+
FloatReg readFloatReg(int floatReg, int width);
FloatReg readFloatReg(int floatReg);
@@ -92,17 +100,17 @@ namespace SparcISA
FloatRegBits readFloatRegBits(int floatReg);
- Fault setFloatReg(int floatReg, const FloatReg &val, int width);
+ void setFloatReg(int floatReg, const FloatReg &val, int width);
- Fault setFloatReg(int floatReg, const FloatReg &val);
+ void setFloatReg(int floatReg, const FloatReg &val);
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
+ void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
+ void setFloatRegBits(int floatReg, const FloatRegBits &val);
IntReg readIntReg(int intReg);
- Fault setIntReg(int intReg, const IntReg &val);
+ void setIntReg(int intReg, const IntReg &val);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 35ff08b43..0d42e2c97 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,5 +31,33 @@
#ifndef __ARCH_SPARC_TLB_HH__
#define __ARCH_SPARC_TLB_HH__
+#include "sim/faults.hh"
+
+class ThreadContext;
+
+namespace SparcISA
+{
+ class TLB
+ {
+ };
+
+ class ITB : public TLB
+ {
+ public:
+ Fault translate(RequestPtr &req, ThreadContext *tc) const
+ {
+ return NoFault;
+ }
+ };
+
+ class DTB : public TLB
+ {
+ public:
+ Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
+ {
+ return NoFault;
+ }
+ };
+}
#endif // __ARCH_SPARC_TLB_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 09:00:44 +0000