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-rw-r--r--src/arch/sparc/SparcNativeTrace.py3
-rw-r--r--src/arch/sparc/SparcSystem.py4
-rw-r--r--src/arch/sparc/SparcTLB.py2
3 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index 46b606652..1dbac34c3 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -28,7 +28,8 @@
from m5.SimObject import SimObject
from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py
index 9d8be5d06..60c56c69b 100644
--- a/src/arch/sparc/SparcSystem.py
+++ b/src/arch/sparc/SparcSystem.py
@@ -28,8 +28,8 @@
from m5.params import *
-from SimpleMemory import SimpleMemory
-from System import System
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.System import System
class SparcSystem(System):
type = 'SparcSystem'
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 219f6842a..a7bfaea2a 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -29,7 +29,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class SparcTLB(BaseTLB):
type = 'SparcTLB'