diff options
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/fpop.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 16 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 25 |
3 files changed, 20 insertions, 23 deletions
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 52193f2c0..97ed40629 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -380,7 +380,7 @@ let {{ class PremFp(FpBinaryOp): code = ''' - MiscReg new_fsw = FSW; + RegVal new_fsw = FSW; int src1_exp; int src2_exp; std::frexp(FpSrcReg1, &src1_exp); diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index b8ceb02ac..4bbe093a4 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -245,7 +245,7 @@ let {{ src2, size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatReg) / srcSize; + int items = sizeof(double) / srcSize; int offset = imm8; if (bits(src1, 0) && (ext & 0x1)) offset -= items; @@ -267,7 +267,7 @@ let {{ src2, size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatReg) / destSize; + int items = sizeof(double) / destSize; int offset = imm8; if (bits(dest, 0) && (ext & 0x1)) offset -= items; @@ -289,7 +289,7 @@ let {{ "InstRegIndex(0)", size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatReg) / srcSize; + int items = sizeof(double) / srcSize; uint64_t result = 0; int offset = (ext & 0x1) ? items : 0; for (int i = 0; i < items; i++) { @@ -325,7 +325,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = sizeof(FloatReg) / size; + int items = sizeof(double) / size; int options; int optionBits; if (size == 8) { @@ -342,7 +342,7 @@ let {{ for (int i = 0; i < items; i++) { uint64_t resBits; uint8_t lsel = sel & mask(optionBits); - if (lsel * size >= sizeof(FloatReg)) { + if (lsel * size >= sizeof(double)) { lsel -= options / 2; resBits = bits(FpSrcReg2_uqw, (lsel + 1) * sizeBits - 1, @@ -367,7 +367,7 @@ let {{ code = ''' assert(srcSize == destSize); int size = destSize; - int items = (sizeof(FloatReg) / size) / 2; + int items = (sizeof(double) / size) / 2; int offset = ext ? items : 0; uint64_t result = 0; for (int i = 0; i < items; i++) { @@ -393,7 +393,7 @@ let {{ op_class = 'SimdMiscOp' code = ''' assert(srcSize == destSize * 2); - int items = (sizeof(FloatReg) / destSize); + int items = (sizeof(double) / destSize); int destBits = destSize * 8; int srcBits = srcSize * 8; uint64_t result = 0; @@ -1091,7 +1091,7 @@ let {{ op_class = 'SimdAddOp' code = ''' int srcBits = srcSize * 8; - int items = sizeof(FloatReg) / srcSize; + int items = sizeof(double) / srcSize; uint64_t sum = 0; for (int i = 0; i < items; i++) { diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 08a4ddd41..6f2901b25 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -51,7 +51,7 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; - IntReg result M5_VAR_USED; + RegVal result M5_VAR_USED; if(%(cond_check)s) { @@ -81,7 +81,7 @@ def template MicroRegOpImmExecute {{ %(op_decl)s; %(op_rd)s; - IntReg result M5_VAR_USED; + RegVal result M5_VAR_USED; if(%(cond_check)s) { @@ -1220,8 +1220,8 @@ let {{ class Wrflags(WrRegOp): code = ''' - MiscReg newFlags = psrc1 ^ op2; - MiscReg userFlagMask = 0xDD5; + RegVal newFlags = psrc1 ^ op2; + RegVal userFlagMask = 0xDD5; // Get only the user flags ccFlagBits = newFlags & ccFlagMask; @@ -1268,8 +1268,8 @@ let {{ class Rflag(RegOp): code = ''' - MiscReg flagMask = 0x3F7FDD5; - MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | + RegVal flagMask = 0x3F7FDD5; + RegVal flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit) & flagMask; int flag = bits(flags, imm8); @@ -1278,8 +1278,8 @@ let {{ ''' big_code = ''' - MiscReg flagMask = 0x3F7FDD5; - MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | + RegVal flagMask = 0x3F7FDD5; + RegVal flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit) & flagMask; int flag = bits(flags, imm8); @@ -1294,7 +1294,7 @@ let {{ class Sext(RegOp): code = ''' - IntReg val = psrc1; + RegVal val = psrc1; // Mask the bit position so that it wraps. int bitPos = op2 & (dataSize * 8 - 1); int sign_bit = bits(val, bitPos, bitPos); @@ -1304,7 +1304,7 @@ let {{ ''' big_code = ''' - IntReg val = psrc1; + RegVal val = psrc1; // Mask the bit position so that it wraps. int bitPos = op2 & (dataSize * 8 - 1); int sign_bit = bits(val, bitPos, bitPos); @@ -1390,10 +1390,7 @@ let {{ if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { fault = std::make_shared<InvalidOpcode>(); } else { - // There are *s in the line below so it doesn't confuse the - // parser. They may be unnecessary. - //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); - MiscReg newVal = psrc1; + RegVal newVal = psrc1; // Check for any modifications that would cause a fault. switch(dest) { |