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-rw-r--r--src/cpu/inorder/cpu.hh9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 34eabbad4..6c1cdc9dc 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -77,7 +77,6 @@ class InOrderCPU : public BaseCPU
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::RegFile RegFile;
- typedef SimpleRenameMap RenameMap;
//DynInstPtr TypeDefs
typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -586,14 +585,6 @@ class InOrderCPU : public BaseCPU
std::list<unsigned> fetchPriorityList;
- /** Rename Map for architectural-to-physical register mappings.
- * In a In-order processor, the mapping is fixed
- * (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
- * In a Out-of-Order processor, this is used to maintain
- * sequential consistency (?right word here?).
- */
- RenameMap renameMap[ThePipeline::MaxThreads];
-
protected:
/** Active Threads List */
std::list<unsigned> activeThreads;