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path: root/src/cpu/inorder/cpu.hh
AgeCommit message (Expand)Author
2015-04-20cpu: Remove the InOrderCPU from the treeAndreas Hansson
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-03-01cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPUChristopher Torng
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu/inorder: merge register class enumsSteve Reinhardt
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-11-01SE/FS: Expose the same methods on the CPUs in SE and FS modes.Gabe Black
2011-10-31SE/FS: Make the functions available from the TC consistent between SE and FS.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-06-19inorder: use trapPending flag to manage trapsKorey Sewell
2011-06-19inorder: dont handle multiple faults on same cycleKorey Sewell
2011-06-19inorder: check for interrupts each tickKorey Sewell
2011-06-19inorder: make InOrder CPU FS compilable/visibleKorey Sewell
2011-06-19inorder: redefine DynInst FP result typeKorey Sewell
2011-06-19inorder: treat SE mode syscalls as a trapping instructionKorey Sewell
2011-06-19imported patch squash_from_next_stageKorey Sewell
2011-06-19inorder: update event prioritiesKorey Sewell
2011-06-19inorder: implement trap handlingKorey Sewell
2011-06-19inorder: use setupSquash for misspeculationKorey Sewell
2011-06-19inorder: simplify handling of split accessesKorey Sewell
2011-06-19inorder: inst. iterator cleanupKorey Sewell
2011-06-19inorder: add types for dependency checksKorey Sewell
2011-06-19inorder: use flattenIdx for reg indexingKorey Sewell
2011-06-19inorder: use m5_hash_map for skedCacheKorey Sewell
2011-04-15includes: sort all includesNathan Binkert
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
2011-02-18inorder: cleanup in destructorsKorey Sewell
2011-02-18inorder: remove reqRemoveListKorey Sewell
2011-02-12inorder: stage scheduler for front/back end schedule creationKorey Sewell
2011-02-12inorder: cache instruction schedulesKorey Sewell
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