1 files changed, 26 insertions, 8 deletions

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 2c79931e2..5b8e02fc6 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -91,15 +103,12 @@ class LSQUnit {
     /** Sets the pointer to the dcache port. */
     void setDcachePort(MasterPort *dcache_port);
 
-    /** Switches out LSQ unit. */
-    void switchOut();
+    /** Perform sanity checks after a drain. */
+    void drainSanityCheck() const;
 
     /** Takes over from another CPU's thread. */
     void takeOverFrom();
 
-    /** Returns if the LSQ is switched out. */
-    bool isSwitchedOut() { return switchedOut; }
-
     /** Ticks the LSQ unit, which in this case only resets the number of
      * used cache ports.
      * @todo: Move the number of used ports up to the LSQ level so it can
@@ -201,12 +210,21 @@ class LSQUnit {
     /** Returns if either the LQ or SQ is full. */
     bool isFull() { return lqFull() || sqFull(); }
 
+    /** Returns if both the LQ and SQ are empty. */
+    bool isEmpty() const { return lqEmpty() && sqEmpty(); }
+
     /** Returns if the LQ is full. */
     bool lqFull() { return loads >= (LQEntries - 1); }
 
     /** Returns if the SQ is full. */
     bool sqFull() { return stores >= (SQEntries - 1); }
 
+    /** Returns if the LQ is empty. */
+    bool lqEmpty() const { return loads == 0; }
+
+    /** Returns if the SQ is empty. */
+    bool sqEmpty() const { return stores == 0; }
+
     /** Returns the number of instructions in the LSQ. */
     unsigned getCount() { return loads + stores; }
 
@@ -225,6 +243,9 @@ class LSQUnit {
     void recvRetry();
 
   private:
+    /** Reset the LSQ state */
+    void resetState();
+
     /** Writes back the instruction, sending it to IEW. */
     void writeback(DynInstPtr &inst, PacketPtr pkt);
 
@@ -420,9 +441,6 @@ class LSQUnit {
     /** The number of used cache ports in this cycle. */
     int usedPorts;
 
-    /** Is the LSQ switched out. */
-    bool switchedOut;
-
     //list<InstSeqNum> mshrSeqNums;
 
     /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */