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-rw-r--r--src/cpu/o3/lsq_unit.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9d885302b..b8e895571 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -610,8 +610,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
Cycles delay(0);
PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
+ data_pkt->dataStatic(load_inst->memData);
if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
- data_pkt->dataStatic(load_inst->memData);
delay = TheISA::handleIprRead(thread, data_pkt);
} else {
assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());