1 files changed, 0 insertions, 94 deletions

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 1c8b98f2e..711447f31 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -141,12 +141,6 @@ class LSQUnit {
      */
     void checkSnoop(PacketPtr pkt);
 
-    // [InvisiSpec] check whether current request will hit in the
-    // spec buffer or not
-    int checkSpecBuffHit(const RequestPtr req, const int req_idx);
-    void setSpecBuffState(const RequestPtr req);
-
-    bool checkPrevLoadsExecuted(const int req_idx);
     /** Executes a load instruction. */
     Fault executeLoad(const DynInstPtr &inst);
 
@@ -165,9 +159,6 @@ class LSQUnit {
     /** Writes back stores. */
     void writebackStores();
 
-    /** [mengjia] Validate loads. */
-    int exposeLoads();
-
     /** [mengjia] Update Visbible State.
      * In the mode defence relying on fence: setup fenceDelay state.
      * In the mode defence relying on invisibleSpec:
@@ -257,9 +248,6 @@ class LSQUnit {
     /** Writes back the instruction, sending it to IEW. */
     void writeback(const DynInstPtr &inst, PacketPtr pkt);
 
-    // [InvisiSpec] complete Validates
-    void completeValidate(DynInstPtr &inst, PacketPtr pkt);
-
     /** Writes back a store that couldn't be completed the previous cycle. */
     void writebackPendingStore();
 
@@ -872,46 +860,12 @@ LSQUnit<Impl>::read(const RequestPtr &req,
         fst_data_pkt = data_pkt;
 
         fst_data_pkt->setFirst();
-        if (sendSpecRead){
-            int src_idx = checkSpecBuffHit(req, load_idx);
-            if (src_idx != -1) {
-                if (allowSpecBuffHit){
-                    data_pkt->setOnlyAccessSpecBuff();
-                }
-                data_pkt->srcIdx = src_idx;
-                specBuffHits++;
-            }else{
-                specBuffMisses++;
-            }
-        }
         fst_data_pkt->reqIdx = load_idx;
     } else {
         // Create the split packets.
         if(sendSpecRead){
-
             fst_data_pkt = Packet::createReadSpec(sreqLow);
-            int fst_src_idx = checkSpecBuffHit(sreqLow, load_idx);
-            if ( fst_src_idx != -1 ) {
-                if (allowSpecBuffHit){
-                    fst_data_pkt->setOnlyAccessSpecBuff();
-                }
-                fst_data_pkt->srcIdx = fst_src_idx;
-                specBuffHits++;
-            } else {
-                specBuffMisses++;
-            }
-
             snd_data_pkt = Packet::createReadSpec(sreqHigh);
-            int snd_src_idx = checkSpecBuffHit(sreqHigh, load_idx);
-            if ( snd_src_idx != -1 ) {
-                if (allowSpecBuffHit){
-                    snd_data_pkt->setOnlyAccessSpecBuff();
-                }
-                snd_data_pkt->srcIdx = snd_src_idx;
-                specBuffHits++;
-            } else {
-                specBuffMisses++;
-            }
         }else{
             fst_data_pkt = Packet::createRead(sreqLow);
             snd_data_pkt = Packet::createRead(sreqHigh);
@@ -1002,58 +956,10 @@ LSQUnit<Impl>::read(const RequestPtr &req,
     // Set everything ready for expose/validation after the read is
     // successfully sent out
     if(sendSpecRead){ // sending actual request
-
-            // [mengjia] Here we set the needExposeOnly flag
-            if (needsTSO && !load_inst->isDataPrefetch()){
-                // need to check whether previous load_instructions specComplete or not
-                if ( checkPrevLoadsExecuted(load_idx) ){
-                    load_inst->needExposeOnly(true);
-                    DPRINTF(LSQUnit, "Set load PC %s, [sn:%lli] as "
-                            "needExposeOnly\n",
-                        load_inst->pcState(), load_inst->seqNum);
-                } else {
-                    DPRINTF(LSQUnit, "Set load PC %s, [sn:%lli] as "
-                            "needValidation\n",
-                        load_inst->pcState(), load_inst->seqNum);
-                }
-            }else{
-                //if RC, always only need expose
-                load_inst->needExposeOnly(true);
-                DPRINTF(LSQUnit, "Set load PC %s, [sn:%lli] as needExposeOnly\n",
-                    load_inst->pcState(), load_inst->seqNum);
-            }
-
-            load_inst->needPostFetch(true);
             assert(!req->isMmappedIpr());
-            //save expose requestPtr
-            if (TheISA::HasUnalignedMemAcc && sreqLow) {
-                load_inst->postSreqLow = std::make_shared<Request>(*sreqLow);
-                load_inst->postSreqHigh = std::make_shared<Request>(*sreqHigh);
-                load_inst->postReq = nullptr;
-                DPRINTF(LSQUnit, "created validation/expose"
-                        " request for inst [sn:%lli]"
-                        " reqLow=%#x, reqHigh=%#x\n",
-                        load_inst->seqNum,
-                        load_inst->postSreqLow->getVaddr(),
-                        load_inst->postSreqHigh->getVaddr());
-            }else{
-                load_inst->postReq = std::make_shared<Request>(*req);
-                load_inst->postSreqLow = nullptr;
-                load_inst->postSreqHigh = nullptr;
-                DPRINTF(LSQUnit, "created validation/expose"
-                        " request for inst [sn:%lli]"
-                        " req=%#x\n",
-                        load_inst->seqNum, load_inst->postReq->getVaddr());
-            }
     } else {
         load_inst->setExposeCompleted();
         load_inst->needPostFetch(false);
-        if (TheISA::HasUnalignedMemAcc && sreqLow) {
-            setSpecBuffState(sreqLow);
-            setSpecBuffState(sreqHigh);
-        } else {
-            setSpecBuffState(req);
-        }
     }
 
     return NoFault;