diff options
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/atomic.hh | 23 | ||||
-rw-r--r-- | src/cpu/simple/base.hh | 14 | ||||
-rw-r--r-- | src/cpu/simple/timing.hh | 21 |
3 files changed, 30 insertions, 28 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 372df7cbd..1a2f19949 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -55,7 +55,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU AtomicSimpleCPU(AtomicSimpleCPUParams *params); virtual ~AtomicSimpleCPU(); - virtual void init(); + void init() override; private: @@ -181,10 +181,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - virtual MasterPort &getDataPort() { return dcachePort; } + MasterPort &getDataPort() override { return dcachePort; } /** Return a reference to the instruction port. */ - virtual MasterPort &getInstPort() { return icachePort; } + MasterPort &getInstPort() override { return icachePort; } /** Perform snoop for other cpu-local thread contexts. */ void threadSnoop(PacketPtr pkt, ThreadID sender); @@ -194,20 +194,21 @@ class AtomicSimpleCPU : public BaseSimpleCPU DrainState drain() override; void drainResume() override; - void switchOut(); - void takeOverFrom(BaseCPU *oldCPU); + void switchOut() override; + void takeOverFrom(BaseCPU *oldCPU) override; - void verifyMemoryMode() const; + void verifyMemoryMode() const override; - virtual void activateContext(ThreadID thread_num); - virtual void suspendContext(ThreadID thread_num); + void activateContext(ThreadID thread_num) override; + void suspendContext(ThreadID thread_num) override; - Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, + unsigned flags) override; Fault writeMem(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Addr addr, unsigned flags, uint64_t *res) override; - virtual void regProbePoints(); + void regProbePoints() override; /** * Print state of address in memory system via PrintReq (for diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 72ac9bb4b..0ec9e502b 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -94,7 +94,7 @@ class BaseSimpleCPU : public BaseCPU BaseSimpleCPU(BaseSimpleCPUParams *params); virtual ~BaseSimpleCPU(); void wakeup(ThreadID tid) override; - virtual void init(); + void init() override; public: Trace::InstRecord *traceData; CheckerCPU *checker; @@ -134,13 +134,13 @@ class BaseSimpleCPU : public BaseCPU void postExecute(); void advancePC(const Fault &fault); - virtual void haltContext(ThreadID thread_num); + void haltContext(ThreadID thread_num) override; // statistics - virtual void regStats(); - virtual void resetStats(); + void regStats() override; + void resetStats() override; - virtual void startup(); + void startup() override; virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, unsigned flags) = 0; @@ -149,8 +149,8 @@ class BaseSimpleCPU : public BaseCPU unsigned flags, uint64_t* res) = 0; void countInst(); - virtual Counter totalInsts() const; - virtual Counter totalOps() const; + Counter totalInsts() const override; + Counter totalOps() const override; void serializeThread(CheckpointOut &cp, ThreadID tid) const override; void unserializeThread(CheckpointIn &cp, ThreadID tid) override; diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index a6c7df988..36e01e9be 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -55,7 +55,7 @@ class TimingSimpleCPU : public BaseSimpleCPU TimingSimpleCPU(TimingSimpleCPUParams * params); virtual ~TimingSimpleCPU(); - virtual void init(); + void init() override; private: @@ -265,28 +265,29 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - virtual MasterPort &getDataPort() { return dcachePort; } + MasterPort &getDataPort() override { return dcachePort; } /** Return a reference to the instruction port. */ - virtual MasterPort &getInstPort() { return icachePort; } + MasterPort &getInstPort() override { return icachePort; } public: DrainState drain() override; void drainResume() override; - void switchOut(); - void takeOverFrom(BaseCPU *oldCPU); + void switchOut() override; + void takeOverFrom(BaseCPU *oldCPU) override; - void verifyMemoryMode() const; + void verifyMemoryMode() const override; - virtual void activateContext(ThreadID thread_num); - virtual void suspendContext(ThreadID thread_num); + void activateContext(ThreadID thread_num) override; + void suspendContext(ThreadID thread_num) override; - Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, + unsigned flags) override; Fault writeMem(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Addr addr, unsigned flags, uint64_t *res) override; void fetch(); void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc); |