diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/base.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index c597ac904..f71277d1c 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -493,7 +493,7 @@ BaseSimpleCPU::preExecute() // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // ALPHA_ISA // check for instruction-count-based events diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index d2107b89a..3090f38a0 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -202,7 +202,7 @@ class SimpleExecContext : public ExecContext { numFpRegReads++; const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** Sets the bits of a floating point register of single width @@ -213,7 +213,7 @@ class SimpleExecContext : public ExecContext { numFpRegWrites++; const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); } /** Reads a vector register. */ |