diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 9 | ||||
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 6 |
2 files changed, 9 insertions, 6 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 50b1b12ce..5b54679c9 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -46,6 +46,7 @@ #ifndef __CPU_BASE_DYN_INST_HH__ #define __CPU_BASE_DYN_INST_HH__ +#include <array> #include <bitset> #include <list> #include <string> @@ -258,22 +259,22 @@ class BaseDynInst : public ExecContext, public RefCounted /** Flattened register index of the destination registers of this * instruction. */ - TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; + std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx; /** Physical register index of the destination registers of this * instruction. */ - PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; + std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx; /** Physical register index of the source registers of this * instruction. */ - PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; + std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx; /** Physical register index of the previous producers of the * architected destinations. */ - PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; + std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx; public: diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 80d502f0e..6740c601d 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -44,6 +44,8 @@ #ifndef __CPU_O3_DYN_INST_HH__ #define __CPU_O3_DYN_INST_HH__ +#include <array> + #include "arch/isa_traits.hh" #include "config/the_isa.hh" #include "cpu/o3/cpu.hh" @@ -108,13 +110,13 @@ class BaseO3DynInst : public BaseDynInst<Impl> protected: /** Values to be written to the destination misc. registers. */ - MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; + std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; /** Indexes of the destination misc. registers. They are needed to defer * the write accesses to the misc. registers until the commit stage, when * the instruction is out of its speculative state. */ - short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; + std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; /** Number of destination misc. registers. */ uint8_t _numDestMiscRegs; |