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-rw-r--r--src/dev/alpha/tsunami_cchip.cc1
-rw-r--r--src/dev/alpha/tsunami_io.cc6
-rw-r--r--src/dev/arm/pl111.cc9
-rw-r--r--src/dev/arm/pl111.hh4
-rw-r--r--src/dev/copy_engine.cc1
-rw-r--r--src/dev/disk_image.cc6
-rw-r--r--src/dev/disk_image.hh2
-rw-r--r--src/dev/ide_ctrl.cc5
-rw-r--r--src/dev/ns_gige.cc42
-rw-r--r--src/dev/pciconfigall.cc2
-rw-r--r--src/dev/pcidev.cc4
11 files changed, 48 insertions, 34 deletions
diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index 74f769c86..0960c71ab 100644
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -53,7 +53,6 @@
#include "params/TsunamiCChip.hh"
#include "sim/system.hh"
-using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
index 0c1937a32..bccdddf85 100644
--- a/src/dev/alpha/tsunami_io.cc
+++ b/src/dev/alpha/tsunami_io.cc
@@ -54,7 +54,11 @@
#include "mem/port.hh"
#include "sim/system.hh"
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::string;
+using std::ostream;
+
//Should this be AlphaISA?
using namespace TheISA;
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 263a3b620..d416ab31f 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -50,6 +50,10 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::vector;
+
using namespace AmbaDev;
// initialize clcd registers
@@ -69,11 +73,12 @@ Pl111::Pl111(const Params *p)
pic = simout.create(csprintf("%s.framebuffer.bmp", sys->name()), true);
- dmaBuffer = new uint8_t[LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t)];
+ const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
+ dmaBuffer = new uint8_t[buffer_size];
memset(lcdPalette, 0, sizeof(lcdPalette));
memset(cursorImage, 0, sizeof(cursorImage));
- memset(dmaBuffer, 0, sizeof(dmaBuffer));
+ memset(dmaBuffer, 0, buffer_size);
if (vncserver)
vncserver->setFramebufferAddr(dmaBuffer);
diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh
index b2dc1f640..e0a03641c 100644
--- a/src/dev/arm/pl111.hh
+++ b/src/dev/arm/pl111.hh
@@ -53,8 +53,6 @@
#include "params/Pl111.hh"
#include "sim/serialize.hh"
-using namespace std;
-
class Gic;
class VncServer;
class Bitmap;
@@ -304,7 +302,7 @@ class Pl111: public AmbaDmaDevice
EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
/** DMA done event */
- vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
+ std::vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
/** Wrapper to create an event out of the interrupt */
EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
diff --git a/src/dev/copy_engine.cc b/src/dev/copy_engine.cc
index 361d4db1b..33994cfde 100644
--- a/src/dev/copy_engine.cc
+++ b/src/dev/copy_engine.cc
@@ -45,7 +45,6 @@
#include "sim/system.hh"
using namespace CopyEngineReg;
-using namespace std;
CopyEngine::CopyEngine(const Params *p)
: PciDev(p)
diff --git a/src/dev/disk_image.cc b/src/dev/disk_image.cc
index 4c770fbcd..c9defb605 100644
--- a/src/dev/disk_image.cc
+++ b/src/dev/disk_image.cc
@@ -170,12 +170,12 @@ CowDiskImage::CowDiskImage(const Params *p)
: DiskImage(p), filename(p->image_file), child(p->child), table(NULL)
{
if (filename.empty()) {
- init(p->table_size);
+ initSectorTable(p->table_size);
} else {
if (!open(filename)) {
if (p->read_only)
fatal("could not open read-only file");
- init(p->table_size);
+ initSectorTable(p->table_size);
}
if (!p->read_only)
@@ -270,7 +270,7 @@ CowDiskImage::open(const string &file)
}
void
-CowDiskImage::init(int hash_size)
+CowDiskImage::initSectorTable(int hash_size)
{
table = new SectorTable(hash_size);
diff --git a/src/dev/disk_image.hh b/src/dev/disk_image.hh
index 3865562a0..1b846522f 100644
--- a/src/dev/disk_image.hh
+++ b/src/dev/disk_image.hh
@@ -121,7 +121,7 @@ class CowDiskImage : public DiskImage
CowDiskImage(const Params *p);
~CowDiskImage();
- void init(int hash_size);
+ void initSectorTable(int hash_size);
bool open(const std::string &file);
void save();
void save(const std::string &file);
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
index 5a663bac9..f33d603af 100644
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -32,7 +32,6 @@
#include <string>
-#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "debug/IdeCtrl.hh"
#include "dev/ide_ctrl.hh"
@@ -42,7 +41,9 @@
#include "params/IdeController.hh"
#include "sim/byteswap.hh"
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::string;
// Bus master IDE registers
enum BMIRegOffset {
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index eb6eb6353..4dc4aeae9 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -50,6 +50,12 @@
#include "params/NSGigE.hh"
#include "sim/system.hh"
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::min;
+using std::ostream;
+using std::string;
+
const char *NsRxStateStrings[] =
{
"rxIdle",
@@ -81,7 +87,6 @@ const char *NsDmaState[] =
"dmaWriteWaiting"
};
-using namespace std;
using namespace Net;
using namespace TheISA;
@@ -479,12 +484,12 @@ NSGigE::write(PacketPtr pkt)
// all these #if 0's are because i don't THINK the kernel needs to
// have these implemented. if there is a problem relating to one of
// these, you may need to add functionality in.
+
+// grouped together and #if 0'ed to avoid empty if body and make clang happy
+#if 0
if (reg & CFGR_TBI_EN) ;
if (reg & CFGR_MODE_1000) ;
- if (reg & CFGR_AUTO_1000)
- panic("CFGR_AUTO_1000 not implemented!\n");
-
if (reg & CFGR_PINT_DUPSTS ||
reg & CFGR_PINT_LNKSTS ||
reg & CFGR_PINT_SPDSTS)
@@ -494,22 +499,11 @@ NSGigE::write(PacketPtr pkt)
if (reg & CFGR_MRM_DIS) ;
if (reg & CFGR_MWI_DIS) ;
- if (reg & CFGR_T64ADDR) ;
- // panic("CFGR_T64ADDR is read only register!\n");
-
- if (reg & CFGR_PCI64_DET)
- panic("CFGR_PCI64_DET is read only register!\n");
-
if (reg & CFGR_DATA64_EN) ;
if (reg & CFGR_M64ADDR) ;
if (reg & CFGR_PHY_RST) ;
if (reg & CFGR_PHY_DIS) ;
- if (reg & CFGR_EXTSTS_EN)
- extstsEnable = true;
- else
- extstsEnable = false;
-
if (reg & CFGR_REQALG) ;
if (reg & CFGR_SB) ;
if (reg & CFGR_POW) ;
@@ -518,6 +512,20 @@ NSGigE::write(PacketPtr pkt)
if (reg & CFGR_BROM_DIS) ;
if (reg & CFGR_EXT_125) ;
if (reg & CFGR_BEM) ;
+
+ if (reg & CFGR_T64ADDR) ;
+ // panic("CFGR_T64ADDR is read only register!\n");
+#endif
+ if (reg & CFGR_AUTO_1000)
+ panic("CFGR_AUTO_1000 not implemented!\n");
+
+ if (reg & CFGR_PCI64_DET)
+ panic("CFGR_PCI64_DET is read only register!\n");
+
+ if (reg & CFGR_EXTSTS_EN)
+ extstsEnable = true;
+ else
+ extstsEnable = false;
break;
case MEAR:
@@ -541,9 +549,13 @@ NSGigE::write(PacketPtr pkt)
eepromClk = reg & MEAR_EECLK;
// since phy is completely faked, MEAR_MD* don't matter
+
+// grouped together and #if 0'ed to avoid empty if body and make clang happy
+#if 0
if (reg & MEAR_MDIO) ;
if (reg & MEAR_MDDIR) ;
if (reg & MEAR_MDC) ;
+#endif
break;
case PTSCR:
diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc
index e7130e11d..320f45543 100644
--- a/src/dev/pciconfigall.cc
+++ b/src/dev/pciconfigall.cc
@@ -43,8 +43,6 @@
#include "params/PciConfigAll.hh"
#include "sim/system.hh"
-using namespace std;
-
PciConfigAll::PciConfigAll(const Params *p)
: PioDevice(p)
{
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 534cbb173..f4728489d 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -52,8 +52,6 @@
#include "sim/byteswap.hh"
#include "sim/core.hh"
-using namespace std;
-
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
int funcid, Platform *p)
@@ -341,7 +339,7 @@ PciDev::writeConfig(PacketPtr pkt)
}
void
-PciDev::serialize(ostream &os)
+PciDev::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 00:06:57 +0000