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-rw-r--r--src/dev/arm/gic_v2.cc3
-rw-r--r--src/dev/arm/gic_v2.hh1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 293c72f1f..1e58718f9 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -622,6 +622,9 @@ GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
case GICC_APR3:
warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
break;
+ case GICC_DIR:
+ warn("GIC DIR write ignored because not implemented: %#x\n", daddr);
+ break;
default:
panic("Tried to write Gic cpu at offset %#x\n", daddr);
break;
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 4afad89f6..49465ad56 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -110,6 +110,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters
GICC_APR2 = 0xd8, // active priority register 2
GICC_APR3 = 0xdc, // active priority register 3
GICC_IIDR = 0xfc, // cpu interface id register
+ GICC_DIR = 0x1000, // deactive interrupt register
};
static const int SGI_MAX = 16; // Number of Software Gen Interrupts