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-rw-r--r--src/mem/Bridge.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 34af552e3..9e86c1a41 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -40,9 +40,9 @@
# Andreas Hansson
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class Bridge(MemObject):
+class Bridge(ClockedObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')