diff options
Diffstat (limited to 'src/mem/Bus.py')
| -rw-r--r-- | src/mem/Bus.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 45b1f1b0a..4637b0ebc 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -45,6 +45,7 @@ from m5.params import * class BaseBus(MemObject): type = 'BaseBus' abstract = True + cxx_header = "mem/bus.hh" slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") header_cycles = Param.Cycles(1, "cycles of overhead per transaction") @@ -66,6 +67,8 @@ class BaseBus(MemObject): class NoncoherentBus(BaseBus): type = 'NoncoherentBus' + cxx_header = "mem/noncoherent_bus.hh" class CoherentBus(BaseBus): type = 'CoherentBus' + cxx_header = "mem/coherent_bus.hh" |