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path: root/src/mem/Bus.py
AgeCommit message (Expand)Author
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20mem: Tie in the snoop filter in the coherent busStephan Diestelhorst
2014-09-20mem: Simple Snoop FilterStephan Diestelhorst
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-07-09Bus: Make the default bus width 8 bytes instead of 64Andreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2010-08-17bus: clean up default responder code.Steve Reinhardt
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert