summaryrefslogtreecommitdiff
path: root/src/mem/cache/prefetch/Prefetcher.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
-rw-r--r--src/mem/cache/prefetch/Prefetcher.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 316a6d0ba..09717dff7 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -65,6 +65,9 @@ class BasePrefetcher(ClockedObject):
]
sys = Param.System(Parent.any, "System this prefetcher belongs to")
+ # Get the block size from the parent (system)
+ block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
+
on_miss = Param.Bool(False, "Only notify prefetcher on misses")
on_read = Param.Bool(True, "Notify prefetcher on reads")
on_write = Param.Bool(True, "Notify prefetcher on writes")
@@ -109,6 +112,9 @@ class StridePrefetcher(QueuedPrefetcher):
cxx_class = 'StridePrefetcher'
cxx_header = "mem/cache/prefetch/stride.hh"
+ # Do not consult stride prefetcher on instruction accesses
+ on_inst = False
+
max_conf = Param.Int(7, "Maximum confidence level")
thresh_conf = Param.Int(4, "Threshold confidence level")
min_conf = Param.Int(0, "Minimum confidence level")