diff options
Diffstat (limited to 'src/mem/cache/prefetch')
| -rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 47 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/base.cc | 8 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/base.hh | 8 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/ghb.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/ghb.hh | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/stride.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/stride.hh | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/tagged.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/tagged.hh | 2 |
9 files changed, 57 insertions, 18 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index fa926e235..e590410ae 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -1,8 +1,48 @@ -from m5.SimObject import SimObject +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +from ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -class BasePrefetcher(SimObject): +class BasePrefetcher(ClockedObject): type = 'BasePrefetcher' abstract = True size = Param.Int(100, @@ -13,8 +53,7 @@ class BasePrefetcher(SimObject): "Squash prefetches with a later time on a subsequent miss") degree = Param.Int(1, "Degree of the prefetch depth") - latency = Param.Latency('10t', - "Latency of the prefetcher") + latency = Param.Cycles('1', "Latency of the prefetcher") use_master_id = Param.Bool(True, "Use the master id to separate calculations of prefetches") data_accesses_only = Param.Bool(False, diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index f3ac5f046..be05a464f 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -45,7 +45,7 @@ #include "sim/system.hh" BasePrefetcher::BasePrefetcher(const Params *p) - : SimObject(p), size(p->size), latency(p->latency), degree(p->degree), + : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree), useMasterId(p->use_master_id), pageStop(!p->cross_pages), serialSquash(p->serial_squash), onlyData(p->data_accesses_only), system(p->sys), masterId(system->getMasterId(name())) @@ -212,11 +212,11 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time) std::list<Addr> addresses; - std::list<Tick> delays; + std::list<Cycles> delays; calculatePrefetch(pkt, addresses, delays); std::list<Addr>::iterator addrIter = addresses.begin(); - std::list<Tick>::iterator delayIter = delays.begin(); + std::list<Cycles>::iterator delayIter = delays.begin(); for (; addrIter != addresses.end(); ++addrIter, ++delayIter) { Addr addr = *addrIter; @@ -241,7 +241,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time) prefetch->req->setThreadContext(pkt->req->contextId(), pkt->req->threadId()); - prefetch->time = time + (*delayIter); // @todo ADD LATENCY HERE + prefetch->time = time + clock * *delayIter; // We just remove the head if we are full if (pf.size() == size) { diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh index 1517be50c..99385c1c1 100644 --- a/src/mem/cache/prefetch/base.hh +++ b/src/mem/cache/prefetch/base.hh @@ -41,11 +41,11 @@ #include "base/statistics.hh" #include "mem/packet.hh" #include "params/BaseCache.hh" -#include "sim/sim_object.hh" +#include "sim/clocked_object.hh" class BaseCache; -class BasePrefetcher : public SimObject +class BasePrefetcher : public ClockedObject { protected: @@ -64,7 +64,7 @@ class BasePrefetcher : public SimObject int blkSize; /** The latency before a prefetch is issued */ - Tick latency; + const Cycles latency; /** The number of prefetches to issue */ unsigned degree; @@ -133,7 +133,7 @@ class BasePrefetcher : public SimObject virtual void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays) = 0; + std::list<Cycles> &delays) = 0; std::list<PacketPtr>::iterator inPrefetch(Addr address); diff --git a/src/mem/cache/prefetch/ghb.cc b/src/mem/cache/prefetch/ghb.cc index 8e42a4e2b..9ceb051a7 100644 --- a/src/mem/cache/prefetch/ghb.cc +++ b/src/mem/cache/prefetch/ghb.cc @@ -40,7 +40,7 @@ void GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays) + std::list<Cycles> &delays) { Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); int master_id = useMasterId ? pkt->req->masterId() : 0; diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh index ff713876a..3e4123de0 100644 --- a/src/mem/cache/prefetch/ghb.hh +++ b/src/mem/cache/prefetch/ghb.hh @@ -57,7 +57,7 @@ class GHBPrefetcher : public BasePrefetcher ~GHBPrefetcher() {} void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays); + std::list<Cycles> &delays); }; #endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__ diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc index feaa9494e..cb67f50f8 100644 --- a/src/mem/cache/prefetch/stride.cc +++ b/src/mem/cache/prefetch/stride.cc @@ -40,7 +40,7 @@ void StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays) + std::list<Cycles> &delays) { if (!pkt->req->hasPC()) { DPRINTF(HWPrefetch, "ignoring request with no PC"); diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh index 51b4252a1..89ac7acad 100644 --- a/src/mem/cache/prefetch/stride.hh +++ b/src/mem/cache/prefetch/stride.hh @@ -75,7 +75,7 @@ class StridePrefetcher : public BasePrefetcher ~StridePrefetcher() {} void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays); + std::list<Cycles> &delays); }; #endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ diff --git a/src/mem/cache/prefetch/tagged.cc b/src/mem/cache/prefetch/tagged.cc index c875b586b..f34b28b14 100644 --- a/src/mem/cache/prefetch/tagged.cc +++ b/src/mem/cache/prefetch/tagged.cc @@ -43,7 +43,7 @@ TaggedPrefetcher::TaggedPrefetcher(const Params *p) void TaggedPrefetcher:: calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays) + std::list<Cycles> &delays) { Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); diff --git a/src/mem/cache/prefetch/tagged.hh b/src/mem/cache/prefetch/tagged.hh index 8037196f8..a93d424e3 100644 --- a/src/mem/cache/prefetch/tagged.hh +++ b/src/mem/cache/prefetch/tagged.hh @@ -49,7 +49,7 @@ class TaggedPrefetcher : public BasePrefetcher ~TaggedPrefetcher() {} void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, - std::list<Tick> &delays); + std::list<Cycles> &delays); }; #endif // __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__ |