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-rw-r--r--src/mem/cache/prefetch/base.cc4
-rw-r--r--src/mem/cache/prefetch/base.hh2
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 57c1424bf..971ecf5b0 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -57,7 +57,8 @@
#include "sim/system.hh"
BasePrefetcher::BasePrefetcher(const Params *p)
- : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
+ : ClockedObject(p), size(p->size), cache(nullptr), blkSize(0),
+ latency(p->latency), degree(p->degree),
useMasterId(p->use_master_id), pageStop(!p->cross_pages),
serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
@@ -69,6 +70,7 @@ BasePrefetcher::BasePrefetcher(const Params *p)
void
BasePrefetcher::setCache(BaseCache *_cache)
{
+ assert(!cache);
cache = _cache;
blkSize = cache->getBlockSize();
}
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index fc0dd0b36..22a4c68f6 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -83,7 +83,7 @@ class BasePrefetcher : public ClockedObject
BaseCache* cache;
/** The block size of the parent cache. */
- int blkSize;
+ unsigned blkSize;
/** The latency before a prefetch is issued */
const Cycles latency;