6 files changed, 99 insertions, 3 deletions
diff --git a/src/sim/SConscript b/src/sim/SConscript
new file mode 100644
index 000000000..46dc2c8dd
--- /dev/null
+++ b/src/sim/SConscript
@@ -0,0 +1,54 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+Source('async.cc')
+Source('builder.cc')
+Source('core.cc')
+Source('debug.cc')
+Source('eventq.cc')
+Source('faults.cc')
+Source('main.cc')
+Source('param.cc')
+Source('root.cc')
+Source('serialize.cc')
+Source('sim_events.cc')
+Source('sim_object.cc')
+Source('simulate.cc')
+Source('startup.cc')
+Source('stat_control.cc')
+Source('system.cc')
+
+if env['FULL_SYSTEM']:
+    Source('pseudo_inst.cc')
+else:
+    Source('process.cc')
+    Source('syscall_emul.cc')
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index bcd0d3df3..65e115256 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -222,7 +222,6 @@ EventQueue::dump()
     cprintf("============================================================\n");
 }
 
-extern "C"
 void
 dumpMainQueue()
 {
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index cea35482a..b09bbc177 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -29,10 +29,13 @@
  *          Gabe Black
  */
 
+#include "arch/isa_traits.hh"
 #include "base/misc.hh"
-#include "sim/faults.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/base.hh"
+#include "sim/faults.hh"
+#include "sim/process.hh"
+#include "mem/page_table.hh"
 
 #if !FULL_SYSTEM
 void FaultBase::invoke(ThreadContext * tc)
@@ -53,3 +56,26 @@ void UnimpFault::invoke(ThreadContext * tc)
 {
     panic("Unimpfault: %s\n", panicStr.c_str());
 }
+#if !FULL_SYSTEM
+void PageTableFault::invoke(ThreadContext *tc)
+{
+    Process *p = tc->getProcessPtr();
+
+    // We've accessed the next page of the stack, so extend the stack
+    // to cover it.
+    if(vaddr < p->stack_min && vaddr >= p->stack_min - TheISA::PageBytes)
+    {
+        p->stack_min -= TheISA::PageBytes;
+        if(p->stack_base - p->stack_min > 8*1024*1024)
+            fatal("Over max stack size for one thread\n");
+        p->pTable->allocate(p->stack_min, TheISA::PageBytes);
+        warn("Increasing stack size by one page.");
+    }
+    // Otherwise, we have an unexpected page fault. Report that fact,
+    // and what address was accessed to cause the fault.
+    else
+    {
+        panic("Page table fault when accessing virtual address %#x\n", vaddr);
+    }
+}
+#endif
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 00264d8fc..2f0b5af62 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -76,4 +76,16 @@ class UnimpFault : public FaultBase
     void invoke(ThreadContext * tc);
 };
 
+#if !FULL_SYSTEM
+class PageTableFault : public FaultBase
+{
+  private:
+    Addr vaddr;
+  public:
+    FaultName name() {return "M5 page table fault";}
+    PageTableFault(Addr va) : vaddr(va) {}
+    void invoke(ThreadContext * tc);
+};
+#endif
+
 #endif // __FAULTS_HH__
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 94ae8e3e6..a3d95b8ec 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -353,6 +353,8 @@ template <typename target_stat, typename host_stat>
 static void
 convertStatBuf(target_stat &tgt, host_stat *host, bool fakeTTY = false)
 {
+    using namespace TheISA;
+
     if (fakeTTY)
         tgt->st_dev = 0xA;
     else
@@ -395,6 +397,8 @@ template <typename target_stat, typename host_stat64>
 static void
 convertStat64Buf(target_stat &tgt, host_stat64 *host, bool fakeTTY = false)
 {
+    using namespace TheISA;
+
     convertStatBuf<target_stat, host_stat64>(tgt, host, fakeTTY);
 #if defined(STAT_HAVE_NSEC)
     tgt->st_atime_nsec = host->st_atime_nsec;
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 1a87e1754..2d0eaaf5b 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -33,6 +33,7 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/remote_gdb.hh"
+#include "arch/utility.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
@@ -203,7 +204,7 @@ System::startup()
 {
     int i;
     for (i = 0; i < threadContexts.size(); i++)
-        threadContexts[i]->activate(0);
+        TheISA::startupCPU(threadContexts[i], i);
 }
 
 void