Age | Commit message (Expand) | Author |
2019-01-22 | sim-se add readv and modifies writev | Brandon Potter |
2019-01-22 | sim-se: add ability to get/set sock metadata | Brandon Potter |
2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
2019-01-22 | sim-se: add calls for network transmissions | Brandon Potter |
2019-01-22 | sim-se: add socket-based functionality | Brandon Potter |
2019-01-18 | base: Fix unitialized storage | Daniel R. Carvalho |
2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
2019-01-10 | sim-se, arch-arm: Add support for getdents64 | Javier Setoain |
2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
2019-01-10 | sim-se: Correctly calculate next PC in clone | Andreas Sandberg |
2019-01-10 | sim-se: Use CONFIG_CLONE_BACKWARDS for Arm | Andreas Sandberg |
2018-12-05 | arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc | Tony Gutierrez |
2018-12-04 | base, sim: Add missing destructors | Nikos Nikoleris |
2018-11-27 | sim-se: only implement getdentsFunc on supported hosts | Ciro Santilli |
2018-11-20 | sim: Deschedule existing events when destructing an event queue. | Gabe Black |
2018-11-14 | sim: Move BitUnion overloading to show/parseParams | Giacomo Travaglini |
2018-11-14 | sim: Move paramIn/Out definition to header file | Giacomo Travaglini |
2018-11-12 | sim: Push the global frequency management code into C++. | Gabe Black |
2018-10-30 | syscall_emul: fix openat when directory does not end in "/" | Ciro Santilli |
2018-10-01 | sim: Extend (UN)SERIALIZE_ARRAY to BitUnions | Giacomo Travaglini |
2018-09-19 | syscall_emul: implement dir-related syscalls | Brandon Potter |
2018-09-19 | syscall_emul: refactor FDEntry and children classes | Brandon Potter |
2018-09-19 | syscall_emul: style changes and FDArray refactor | Brandon Potter |
2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
2018-09-14 | power: Add a clock_period variable to power expressions | Sherif Elhabbal |
2018-09-11 | base: Correct a small typo in sim/core.(hh|cc). | Gabe Black |
2018-09-07 | sim: Add System method for MasterID lookup | Giacomo Travaglini |
2018-06-25 | syscall_emul: adding symlink system call | Matt Sinclair |
2018-06-25 | syscall_emul: adding link system call | Matt Sinclair |
2018-05-30 | dev: Exit correctly in dist-gem5 for SE mode | Michael LeBeane |
2018-05-16 | style: fix amd license and style issues | Tony Gutierrez |
2018-05-09 | sim: Remove trailing dot when assigning a master's name | Giacomo Travaglini |
2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
2018-04-20 | docs: Fix power model doxygen | Jason Lowe-Power |
2018-03-15 | sim-se: Fix fallthrough in prlimit | Jason Lowe-Power |
2018-02-28 | sim, power: Temperature used for power calculations | Anouk Van Laer |
2018-02-28 | sim: Added model type to power model | Anouk Van Laer |
2018-02-16 | sim: Add gtoh/htog helpers that take an explicit endianness | Chuan Zhu |
2018-02-09 | sim: Remove _numContexts member in System class | Giacomo Travaglini |
2018-01-29 | arm: DT autogeneration - Device Tree generation methods | Glenn Bergmans |
2018-01-23 | tarch, mem: Abstract the data stored in the SE page tables. | Gabe Black |
2018-01-23 | x86, mem: Rewrite the multilevel page table class. | Gabe Black |
2018-01-20 | sim: Use the new BitUnion templates in serialize.hh. | Gabe Black |
2018-01-20 | base: Rework bitunions so they can be more flexible. | Gabe Black |
2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
2018-01-16 | sim: Simplify registerThreadContext a little bit. | Gabe Black |
2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
2018-01-10 | arch-riscv,sim: Support clone syscall in RISC-V | Tuan Ta |
2018-01-05 | sim: Fix a bug in prlimit syscall in SE mode | Tuan Ta |