summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/fastmodel/iris/cpu.cc7
-rw-r--r--src/arch/arm/fastmodel/iris/cpu.hh2
2 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc
index e5d95ef65..6c282b69a 100644
--- a/src/arch/arm/fastmodel/iris/cpu.cc
+++ b/src/arch/arm/fastmodel/iris/cpu.cc
@@ -31,6 +31,7 @@
#include "arch/arm/fastmodel/iris/thread_context.hh"
#include "scx/scx.h"
+#include "sim/serialize.hh"
namespace Iris
{
@@ -93,4 +94,10 @@ BaseCPU::init()
tc->initMemProxies(tc);
}
+void
+BaseCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
+{
+ ::serialize(*threadContexts[tid], cp);
+}
+
} // namespace Iris
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index 0d15fc82a..3b913b92d 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -118,6 +118,8 @@ class BaseCPU : public ::BaseCPU
}
void init() override;
+
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
};
// This class specializes the one above and sets up ThreadContexts based on