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-rw-r--r--src/cpu/testers/traffic_gen/base.cc5
-rw-r--r--src/cpu/testers/traffic_gen/base.hh5
-rw-r--r--src/cpu/testers/traffic_gen/dram_gen.cc25
-rw-r--r--src/cpu/testers/traffic_gen/dram_gen.hh8
-rw-r--r--src/cpu/testers/traffic_gen/dram_rot_gen.cc10
-rw-r--r--src/cpu/testers/traffic_gen/dram_rot_gen.hh6
-rw-r--r--src/cpu/testers/traffic_gen/traffic_gen.cc8
7 files changed, 32 insertions, 35 deletions
diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc
index 266f46155..2359eeaec 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -55,6 +55,7 @@
#include "cpu/testers/traffic_gen/stream_gen.hh"
#include "debug/Checkpoint.hh"
#include "debug/TrafficGen.hh"
+#include "enums/AddrMap.hh"
#include "params/BaseTrafficGen.hh"
#include "sim/sim_exit.hh"
#include "sim/stats.hh"
@@ -404,7 +405,7 @@ BaseTrafficGen::createDram(Tick duration,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
{
return std::shared_ptr<BaseGen>(new DramGen(*this, masterID,
@@ -429,7 +430,7 @@ BaseTrafficGen::createDramRot(Tick duration,
unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
{
diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh
index 0d6784e40..0a95136a0 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -47,6 +47,7 @@
#include <unordered_map>
#include "base/statistics.hh"
+#include "enums/AddrMap.hh"
#include "mem/qport.hh"
#include "sim/clocked_object.hh"
@@ -278,7 +279,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
std::shared_ptr<BaseGen> createDramRot(
@@ -288,7 +289,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank);
diff --git a/src/cpu/testers/traffic_gen/dram_gen.cc b/src/cpu/testers/traffic_gen/dram_gen.cc
index d061f6cab..126947244 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.cc
+++ b/src/cpu/testers/traffic_gen/dram_gen.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
-
+#include "enums/AddrMap.hh"
DramGen::DramGen(SimObject &obj,
MasterID master_id, Tick _duration,
@@ -58,7 +58,7 @@ DramGen::DramGen(SimObject &obj,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
: RandomGen(obj, master_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
@@ -73,11 +73,6 @@ DramGen::DramGen(SimObject &obj,
rankBits(floorLog2(nbr_of_ranks)),
nbrOfRanks(nbr_of_ranks)
{
- if (addrMapping != 1 && addrMapping != 0) {
- addrMapping = 1;
- warn("Unknown address mapping specified, using RoRaBaCoCh\n");
- }
-
if (nbr_of_banks_util > nbr_of_banks_DRAM)
fatal("Attempting to use more banks (%d) than "
"what is available (%d)\n",
@@ -115,14 +110,13 @@ DramGen::getNextPacket()
} else {
// increment the column by one
- if (addrMapping == 1)
- // addrMapping=1: RoRaBaCoCh/RoRaBaChCo
+ if (addrMapping == Enums::RoRaBaCoCh ||
+ addrMapping == Enums::RoRaBaChCo)
// Simply increment addr by blocksize to increment
// the column by one
addr += blocksize;
- else if (addrMapping == 0) {
- // addrMapping=0: RoCoRaBaCh
+ else if (addrMapping == Enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /
nbrOfBanksDRAM / nbrOfRanks) %
@@ -177,8 +171,8 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
unsigned int new_col =
random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
- if (addrMapping == 1) {
- // addrMapping=1: RoRaBaCoCh/RoRaBaChCo
+ if (addrMapping == Enums::RoRaBaCoCh ||
+ addrMapping == Enums::RoRaBaChCo) {
// Block bits, then page bits, then bank bits, then rank bits
replaceBits(addr, blockBits + pageBits + bankBits - 1,
blockBits + pageBits, new_bank);
@@ -187,8 +181,7 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
blockBits + pageBits + bankBits, new_rank);
}
- } else if (addrMapping == 0) {
- // addrMapping=0: RoCoRaBaCh
+ } else if (addrMapping == Enums::RoCoRaBaCh) {
// Block bits, then bank bits, then rank bits, then page bits
replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
diff --git a/src/cpu/testers/traffic_gen/dram_gen.hh b/src/cpu/testers/traffic_gen/dram_gen.hh
index 8b9efb747..fde24312c 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_gen.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -51,6 +51,7 @@
#include "base/bitfield.hh"
#include "base/intmath.hh"
+#include "enums/AddrMap.hh"
#include "mem/packet.hh"
#include "random_gen.hh"
@@ -84,7 +85,6 @@ class DramGen : public RandomGen
* @param nbr_of_banks_util Number of banks to utilized,
* for N banks, we will use banks: 0->(N-1)
* @param addr_mapping Address mapping to be used,
- * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramGen(SimObject &obj,
@@ -95,7 +95,7 @@ class DramGen : public RandomGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
PacketPtr getNextPacket();
@@ -141,7 +141,7 @@ class DramGen : public RandomGen
const unsigned int nbrOfBanksUtil;
/** Address mapping to be used */
- unsigned int addrMapping;
+ Enums::AddrMap addrMapping;
/** Number of rank bits in DRAM address*/
const unsigned int rankBits;
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.cc b/src/cpu/testers/traffic_gen/dram_rot_gen.cc
index 103ff4d86..d3e197737 100644
--- a/src/cpu/testers/traffic_gen/dram_rot_gen.cc
+++ b/src/cpu/testers/traffic_gen/dram_rot_gen.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2017 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2017, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,6 +47,7 @@
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
+#include "enums/AddrMap.hh"
PacketPtr
DramRotGen::getNextPacket()
@@ -102,14 +103,13 @@ DramRotGen::getNextPacket()
} else {
// increment the column by one
- if (addrMapping == 1)
- // addrMapping=1: RoRaBaCoCh/RoRaBaChCo
+ if (addrMapping == Enums::RoRaBaCoCh ||
+ addrMapping == Enums::RoRaBaChCo)
// Simply increment addr by blocksize to
// increment the column by one
addr += blocksize;
- else if (addrMapping == 0) {
- // addrMapping=0: RoCoRaBaCh
+ else if (addrMapping == Enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.hh b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
index 59a1bc2fa..2c3f9db80 100644
--- a/src/cpu/testers/traffic_gen/dram_rot_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -52,6 +52,7 @@
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "dram_gen.hh"
+#include "enums/AddrMap.hh"
#include "mem/packet.hh"
class DramRotGen : public DramGen
@@ -84,7 +85,6 @@ class DramRotGen : public DramGen
* for N banks, we will use banks: 0->(N-1)
* @param nbr_of_ranks Number of ranks utilized,
* @param addr_mapping Address mapping to be used,
- * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
@@ -94,7 +94,7 @@ class DramRotGen : public DramGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
- unsigned int addr_mapping,
+ Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
: DramGen(obj, master_id, _duration, start_addr, end_addr,
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc
index db1569b04..298e3ea2f 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -223,12 +223,14 @@ TrafficGen::parseConfig()
unsigned int page_size;
unsigned int nbr_of_banks_DRAM;
unsigned int nbr_of_banks_util;
- unsigned int addr_mapping;
+ unsigned _addr_mapping;
unsigned int nbr_of_ranks;
is >> stride_size >> page_size >> nbr_of_banks_DRAM >>
- nbr_of_banks_util >> addr_mapping >>
+ nbr_of_banks_util >> _addr_mapping >>
nbr_of_ranks;
+ Enums::AddrMap addr_mapping =
+ static_cast<Enums::AddrMap>(_addr_mapping);
if (stride_size > page_size)
warn("DRAM generator stride size (%d) is greater "
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 18:30:31 +0000