5 files changed, 52 insertions, 21 deletions

diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index e78e7ede5..43c658830 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -58,6 +58,7 @@
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/profiler/AddressProfiler.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/system/Sequencer.hh"
 #include "mem/ruby/system/System.hh"
 
 using namespace std;
@@ -171,7 +172,7 @@ Profiler::print(ostream& out) const
 }
 
 void
-Profiler::printRequestProfile(ostream &out)
+Profiler::printRequestProfile(ostream &out) const
 {
     out << "Request vs. RubySystem State Profile" << endl;
     out << "--------------------------------" << endl;
@@ -224,7 +225,7 @@ Profiler::printRequestProfile(ostream &out)
 }
 
 void
-Profiler::printDelayProfile(ostream &out)
+Profiler::printDelayProfile(ostream &out) const
 {
     out << "Message Delayed Cycles" << endl;
     out << "----------------------" << endl;
@@ -256,6 +257,28 @@ Profiler::printDelayProfile(ostream &out)
 }
 
 void
+Profiler::printOutstandingReqProfile(ostream &out) const
+{
+    Histogram sequencerRequests;
+
+    for (uint32_t i = 0; i < MachineType_NUM; i++) {
+        for (map<uint32_t, AbstractController*>::iterator it =
+                  g_abs_controls[i].begin();
+             it != g_abs_controls[i].end(); ++it) {
+
+            AbstractController *ctr = (*it).second;
+            Sequencer *seq = ctr->getSequencer();
+            if (seq != NULL) {
+                sequencerRequests.add(seq->getOutstandReqHist());
+            }
+        }
+    }
+
+    out << "sequencer_requests_outstanding: "
+        << sequencerRequests << endl;
+}
+
+void
 Profiler::printStats(ostream& out, bool short_stats)
 {
     out << endl;
@@ -344,8 +367,7 @@ Profiler::printStats(ostream& out, bool short_stats)
         out << "Busy Bank Count:" << m_busyBankCount << endl;
         out << endl;
 
-        out << "sequencer_requests_outstanding: "
-            << m_sequencer_requests << endl;
+        printOutstandingReqProfile(out);
         out << endl;
     }
 
@@ -548,7 +570,6 @@ Profiler::clearStats()
     }
     m_allSWPrefetchLatencyHistogram.clear(200);
 
-    m_sequencer_requests.clear();
     m_read_sharing_histogram.clear();
     m_write_sharing_histogram.clear();
     m_all_sharing_histogram.clear();
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 421e8fe55..aabe7bfaa 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -144,8 +144,6 @@ class Profiler : public SimObject
     void swPrefetchLatency(Cycles t, RubyRequestType type,
                            const GenericMachineType respondingMach);
 
-    void sequencerRequests(int num) { m_sequencer_requests.add(num); }
-
     void print(std::ostream& out) const;
 
     void rubyWatch(int proc);
@@ -159,8 +157,9 @@ class Profiler : public SimObject
     bool getAllInstructions() { return m_all_instructions; }
 
   private:
-    void printRequestProfile(std::ostream &out);
-    void printDelayProfile(std::ostream &out);
+    void printRequestProfile(std::ostream &out) const;
+    void printDelayProfile(std::ostream &out) const;
+    void printOutstandingReqProfile(std::ostream &out) const;
 
   private:
     // Private copy constructor and assignment operator
@@ -185,7 +184,6 @@ class Profiler : public SimObject
     Histogram m_filter_action_histogram;
     Histogram m_tbeProfile;
 
-    Histogram m_sequencer_requests;
     Histogram m_read_sharing_histogram;
     Histogram m_write_sharing_histogram;
     Histogram m_all_sharing_histogram;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 13107038c..6e99a72bb 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -27,6 +27,7 @@
  */
 
 #include "mem/ruby/slicc_interface/AbstractController.hh"
+#include "mem/ruby/system/Sequencer.hh"
 #include "mem/ruby/system/System.hh"
 
 AbstractController::AbstractController(const Params *p)
@@ -60,6 +61,11 @@ AbstractController::clearStats()
     for (uint32_t i = 0; i < size; i++) {
         m_delayVCHistogram[i].clear();
     }
+
+    Sequencer *seq = getSequencer();
+    if (seq != NULL) {
+        seq->clearStats();
+    }
 }
 
 void
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 54fb83dd0..5eacc976a 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -133,6 +133,11 @@ Sequencer::wakeup()
     }
 }
 
+void Sequencer::clearStats()
+{
+    m_outstandReqHist.clear();
+}
+
 void
 Sequencer::printStats(ostream & out) const
 {
@@ -268,7 +273,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
         }
     }
 
-    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
+    m_outstandReqHist.add(m_outstanding_count);
     assert(m_outstanding_count ==
         (m_writeRequestTable.size() + m_readRequestTable.size()));
 
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 782b776f9..058edb9ce 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -68,6 +68,8 @@ class Sequencer : public RubyPort
 
     void printProgress(std::ostream& out) const;
 
+    void clearStats();
+
     void writeCallback(const Address& address, DataBlock& data);
 
     void writeCallback(const Address& address,
@@ -97,17 +99,12 @@ class Sequencer : public RubyPort
     RequestStatus makeRequest(PacketPtr pkt);
     bool empty() const;
     int outstandingCount() const { return m_outstanding_count; }
-    bool
-    isDeadlockEventScheduled() const
-    {
-        return deadlockCheckEvent.scheduled();
-    }
 
-    void
-    descheduleDeadlockEvent()
-    {
-        deschedule(deadlockCheckEvent);
-    }
+    bool isDeadlockEventScheduled() const
+    { return deadlockCheckEvent.scheduled(); }
+
+    void descheduleDeadlockEvent()
+    { deschedule(deadlockCheckEvent); }
 
     void print(std::ostream& out) const;
     void printStats(std::ostream& out) const;
@@ -119,6 +116,7 @@ class Sequencer : public RubyPort
     void invalidateSC(const Address& address);
 
     void recordRequestType(SequencerRequestType requestType);
+    Histogram& getOutstandReqHist() { return m_outstandReqHist; }
 
   private:
     void issueRequest(PacketPtr pkt, RubyRequestType type);
@@ -160,6 +158,9 @@ class Sequencer : public RubyPort
 
     bool m_usingNetworkTester;
 
+    //! Histogram for number of outstanding requests per cycle.
+    Histogram m_outstandReqHist;
+
     class SequencerWakeupEvent : public Event
     {
       private: