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-rw-r--r--src/arch/arm/isa.hh2
-rw-r--r--src/cpu/reg_class.hh2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 0521c43f9..7b39682f9 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -461,7 +461,7 @@ namespace ArmISA
return INTREG_SP0;
default:
panic("Invalid exception level");
- break;
+ return 0; // Never happens.
}
} else {
return flattenIntRegModeIndex(reg);
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 617d17e35..69da9cf7e 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -84,7 +84,7 @@ class RegId {
static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
friend struct std::hash<RegId>;
public:
- RegId() {};
+ RegId() : regClass(IntRegClass), regIdx(0), elemIdx(-1) {}
RegId(RegClass reg_class, RegIndex reg_idx)
: regClass(reg_class), regIdx(reg_idx), elemIdx(-1)
{