diff options
Diffstat (limited to 'src')
| -rwxr-xr-x | src/arch/isa_parser.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 95c57af2f..754a64fdb 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Steve Reinhardt -# Gabe Black # Korey Sewell import os @@ -1411,6 +1410,9 @@ class ControlRegOperand(Operand): error(0, 'Attempt to write control register as FP') wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + self.base_name + return wb class ControlBitfieldOperand(ControlRegOperand): def makeRead(self): |