diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/SConscript | 5 | ||||
| -rw-r--r-- | src/cpu/SConscript | 30 | ||||
| -rw-r--r-- | src/cpu/base_dyn_inst_impl.hh (renamed from src/cpu/base_dyn_inst.cc) | 26 | ||||
| -rw-r--r-- | src/cpu/checker/cpu_impl.hh (renamed from src/cpu/checker/cpu.cc) | 14 | ||||
| -rw-r--r-- | src/cpu/o3/base_dyn_inst.cc | 40 | ||||
| -rw-r--r-- | src/cpu/o3/bpred_unit.cc | 4 | ||||
| -rw-r--r-- | src/cpu/o3/checker_builder.cc (renamed from src/cpu/checker/o3_builder.cc) | 5 | ||||
| -rw-r--r-- | src/cpu/ozone/bpred_unit.cc | 36 | ||||
| -rw-r--r-- | src/cpu/ozone/checker_builder.cc (renamed from src/cpu/checker/ozone_builder.cc) | 5 | ||||
| -rw-r--r-- | src/cpu/ozone/ozone_base_dyn_inst.cc | 39 | ||||
| -rw-r--r-- | src/cpu/ozone/simple_base_dyn_inst.cc | 39 | ||||
| -rw-r--r-- | src/python/m5/__init__.py | 88 |
12 files changed, 224 insertions, 107 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index ff460dafd..bc517341a 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -128,6 +128,11 @@ isa_desc_gen_files = Split('decoder.cc decoder.hh') isa_desc_gen_files += [CpuModel.dict[cpu].filename for cpu in env['CPU_MODELS']] +# Also include the CheckerCPU as one of the models if it is being +# enabled via command line. +if env['USE_CHECKER']: + isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename] + # The emitter patches up the sources & targets to include the # autogenerated files as targets and isa parser itself as a source. def isa_desc_emitter(target, source, env): diff --git a/src/cpu/SConscript b/src/cpu/SConscript index f855682a1..eea9ba64b 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -68,6 +68,13 @@ mem_comp_sig_template = ''' virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; }; ''' +# Generate a temporary CPU list, including the CheckerCPU if +# it's enabled. This isn't used for anything else other than StaticInst +# headers. +temp_cpu_list = env['CPU_MODELS'] +if env['USE_CHECKER']: + temp_cpu_list.append('CheckerCPU') + # Generate header. def gen_cpu_exec_signatures(target, source, env): f = open(str(target[0]), 'w') @@ -75,7 +82,7 @@ def gen_cpu_exec_signatures(target, source, env): #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ #define __CPU_STATIC_INST_EXEC_SIGS_HH__ ''' - for cpu in env['CPU_MODELS']: + for cpu in temp_cpu_list: xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] print >> f, exec_sig_template % (xc_type, xc_type, xc_type) print >> f, ''' @@ -85,12 +92,14 @@ def gen_cpu_exec_signatures(target, source, env): # Generate string that gets printed when header is rebuilt def gen_sigs_string(target, source, env): return "Generating static_inst_exec_sigs.hh: " \ - + ', '.join(env['CPU_MODELS']) + + ', '.join(temp_cpu_list) # Add command to generate header to environment. env.Command('static_inst_exec_sigs.hh', models_db, Action(gen_cpu_exec_signatures, gen_sigs_string, - varlist = ['CPU_MODELS'])) + varlist = temp_cpu_list)) + +env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) # List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True # and one of these are not being used. @@ -122,11 +131,11 @@ if 'FastCPU' in env['CPU_MODELS']: if 'AlphaO3CPU' in env['CPU_MODELS']: sources += Split(''' - base_dyn_inst.cc o3/2bit_local_pred.cc o3/alpha_dyn_inst.cc o3/alpha_cpu.cc o3/alpha_cpu_builder.cc + o3/base_dyn_inst.cc o3/bpred_unit.cc o3/btb.cc o3/commit.cc @@ -148,8 +157,8 @@ if 'AlphaO3CPU' in env['CPU_MODELS']: o3/store_set.cc o3/tournament_pred.cc ''') - if 'CheckerCPU' in env['CPU_MODELS']: - sources += Split('checker/o3_builder.cc') + if env['USE_CHECKER']: + sources += Split('o3/checker_builder.cc') if 'OzoneSimpleCPU' in env['CPU_MODELS']: sources += Split(''' @@ -161,18 +170,19 @@ if 'OzoneSimpleCPU' in env['CPU_MODELS']: ozone/inst_queue.cc ozone/rename_table.cc ''') - if 'CheckerCPU' in env['CPU_MODELS']: - sources += Split('checker/ozone_builder.cc') if 'OzoneCPU' in env['CPU_MODELS']: sources += Split(''' + ozone/base_dyn_inst.cc + ozone/bpred_unit.cc ozone/lsq_unit.cc ozone/lw_back_end.cc ozone/lw_lsq.cc ''') + if env['USE_CHECKER']: + sources += Split('ozone/checker_builder.cc') -if 'CheckerCPU' in env['CPU_MODELS']: - sources += Split('checker/cpu.cc') +if env['USE_CHECKER']: checker_supports = False for i in CheckerSupportedCPUList: if i in env['CPU_MODELS']: diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst_impl.hh index 5e2a6392a..91424faad 100644 --- a/src/cpu/base_dyn_inst.cc +++ b/src/cpu/base_dyn_inst_impl.hh @@ -41,10 +41,6 @@ #include "mem/request.hh" #include "cpu/base_dyn_inst.hh" -#include "cpu/o3/alpha_impl.hh" -#include "cpu/o3/alpha_cpu.hh" -//#include "cpu/ozone/simple_impl.hh" -//#include "cpu/ozone/ozone_impl.hh" using namespace std; using namespace TheISA; @@ -301,25 +297,3 @@ BaseDynInst<Impl>::eaSrcsReady() return true; } - -// Forward declaration -template class BaseDynInst<AlphaSimpleImpl>; - -template <> -int -BaseDynInst<AlphaSimpleImpl>::instcount = 0; -/* -// Forward declaration -template class BaseDynInst<SimpleImpl>; - -template <> -int -BaseDynInst<SimpleImpl>::instcount = 0; - -// Forward declaration -template class BaseDynInst<OzoneImpl>; - -template <> -int -BaseDynInst<OzoneImpl>::instcount = 0; -*/ diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu_impl.hh index 45c57d276..5091c7c1a 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu_impl.hh @@ -43,16 +43,10 @@ #include "sim/sim_object.hh" #include "sim/stats.hh" -#include "cpu/o3/alpha_dyn_inst.hh" -#include "cpu/o3/alpha_impl.hh" - -//#include "cpu/ozone/dyn_inst.hh" -//#include "cpu/ozone/ozone_impl.hh" -//#include "cpu/ozone/simple_impl.hh" - #if FULL_SYSTEM #include "sim/system.hh" #include "arch/vtophys.hh" +#include "kern/kernel_stats.hh" #endif // FULL_SYSTEM using namespace std; @@ -826,9 +820,3 @@ Checker<DynInstPtr>::dumpInsts() } } - -//template -//class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >; -// Manually instantiate checker -template -class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >; diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc new file mode 100644 index 000000000..1f7540d6a --- /dev/null +++ b/src/cpu/o3/base_dyn_inst.cc @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#include "cpu/base_dyn_inst_impl.hh" +#include "cpu/o3/alpha_cpu.hh" +#include "cpu/o3/alpha_impl.hh" + +// Explicit instantiation +template class BaseDynInst<AlphaSimpleImpl>; + +template <> +int +BaseDynInst<AlphaSimpleImpl>::instcount = 0; diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc index 294438704..c35c0a0aa 100644 --- a/src/cpu/o3/bpred_unit.cc +++ b/src/cpu/o3/bpred_unit.cc @@ -31,9 +31,5 @@ #include "cpu/o3/bpred_unit_impl.hh" #include "cpu/o3/alpha_impl.hh" #include "cpu/o3/alpha_dyn_inst.hh" -//#include "cpu/ozone/ozone_impl.hh" -//#include "cpu/ozone/simple_impl.hh" template class BPredUnit<AlphaSimpleImpl>; -//template class BPredUnit<OzoneImpl>; -//template class BPredUnit<SimpleImpl>; diff --git a/src/cpu/checker/o3_builder.cc b/src/cpu/o3/checker_builder.cc index 534a5e28c..58c40d00c 100644 --- a/src/cpu/checker/o3_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -30,7 +30,7 @@ #include <string> -#include "cpu/checker/cpu.hh" +#include "cpu/checker/cpu_impl.hh" #include "cpu/inst_seq.hh" #include "cpu/o3/alpha_dyn_inst.hh" #include "cpu/o3/alpha_impl.hh" @@ -40,6 +40,9 @@ class MemObject; +template +class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >; + /** * Specific non-templated derived class used for SimObject configuration. */ diff --git a/src/cpu/ozone/bpred_unit.cc b/src/cpu/ozone/bpred_unit.cc new file mode 100644 index 000000000..835324ce1 --- /dev/null +++ b/src/cpu/ozone/bpred_unit.cc @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2004-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#include "cpu/o3/bpred_unit_impl.hh" +#include "cpu/ozone/ozone_impl.hh" +#include "cpu/ozone/simple_impl.hh" + +template class BPredUnit<OzoneImpl>; +template class BPredUnit<SimpleImpl>; diff --git a/src/cpu/checker/ozone_builder.cc b/src/cpu/ozone/checker_builder.cc index 3c43ab503..f6786f24b 100644 --- a/src/cpu/checker/ozone_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -30,7 +30,7 @@ #include <string> -#include "cpu/checker/cpu.hh" +#include "cpu/checker/cpu_impl.hh" #include "cpu/inst_seq.hh" #include "cpu/ozone/dyn_inst.hh" #include "cpu/ozone/ozone_impl.hh" @@ -39,6 +39,9 @@ #include "sim/process.hh" #include "sim/sim_object.hh" +template +class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >; + /** * Specific non-templated derived class used for SimObject configuration. */ diff --git a/src/cpu/ozone/ozone_base_dyn_inst.cc b/src/cpu/ozone/ozone_base_dyn_inst.cc new file mode 100644 index 000000000..5a3a69dff --- /dev/null +++ b/src/cpu/ozone/ozone_base_dyn_inst.cc @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#include "cpu/base_dyn_inst_impl.hh" +#include "cpu/ozone/ozone_impl.hh" + +// Explicit instantiation +template class BaseDynInst<OzoneImpl>; + +template <> +int +BaseDynInst<OzoneImpl>::instcount = 0; diff --git a/src/cpu/ozone/simple_base_dyn_inst.cc b/src/cpu/ozone/simple_base_dyn_inst.cc new file mode 100644 index 000000000..fdaeaf57e --- /dev/null +++ b/src/cpu/ozone/simple_base_dyn_inst.cc @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#include "cpu/base_dyn_inst_impl.hh" +#include "cpu/ozone/simple_impl.hh" + +// Explicit instantiation +template class BaseDynInst<SimpleImpl>; + +template <> +int +BaseDynInst<SimpleImpl>::instcount = 0; diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index ac6904277..a7e653fc2 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -84,32 +84,32 @@ def setTraceStart(option, opt_str, value, parser): def setTraceFile(option, opt_str, value, parser): objects.Trace.file = value -def usePCSymbol(option, opt_str, value, parser): - objects.ExecutionTrace.pc_symbol = value +def noPCSymbol(option, opt_str, value, parser): + objects.ExecutionTrace.pc_symbol = False -def printCycle(option, opt_str, value, parser): - objects.ExecutionTrace.print_cycle = value +def noPrintCycle(option, opt_str, value, parser): + objects.ExecutionTrace.print_cycle = False -def printOp(option, opt_str, value, parser): - objects.ExecutionTrace.print_opclass = value +def noPrintOpclass(option, opt_str, value, parser): + objects.ExecutionTrace.print_opclass = False -def printThread(option, opt_str, value, parser): - objects.ExecutionTrace.print_thread = value +def noPrintThread(option, opt_str, value, parser): + objects.ExecutionTrace.print_thread = False -def printEA(option, opt_str, value, parser): - objects.ExecutionTrace.print_effaddr = value +def noPrintEA(option, opt_str, value, parser): + objects.ExecutionTrace.print_effaddr = False -def printData(option, opt_str, value, parser): - objects.ExecutionTrace.print_data = value +def noPrintData(option, opt_str, value, parser): + objects.ExecutionTrace.print_data = False def printFetchseq(option, opt_str, value, parser): - objects.ExecutionTrace.print_fetchseq = value + objects.ExecutionTrace.print_fetchseq = True def printCpseq(option, opt_str, value, parser): - objects.ExecutionTrace.print_cpseq = value + objects.ExecutionTrace.print_cpseq = True def dumpOnExit(option, opt_str, value, parser): - objects.Trace.dump_on_exit = value + objects.Trace.dump_on_exit = True def debugBreak(option, opt_str, value, parser): objects.Debug.break_cycles = value @@ -131,47 +131,31 @@ standardOptions = [ callback=setTraceStart), optparse.make_option("--tracefile", type="string", action="callback", callback=setTraceFile), - optparse.make_option("--pcsymbol", type="choice", choices=TrueOrFalse, - default="True", metavar=TorF, - action="callback", callback=usePCSymbol, - help="Use PC symbols in trace output"), - optparse.make_option("--printcycle", type="choice", choices=TrueOrFalse, - default="True", metavar=TorF, - action="callback", callback=printCycle, - help="Print cycle numbers in trace output"), - optparse.make_option("--printopclass", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, - action="callback", callback=printOp, - help="Print cycle numbers in trace output"), - optparse.make_option("--printthread", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, - action="callback", callback=printThread, - help="Print thread number in trace output"), - optparse.make_option("--printeffaddr", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, - action="callback", callback=printEA, - help="Print effective address in trace output"), - optparse.make_option("--printdata", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, - action="callback", callback=printData, - help="Print result data in trace output"), - optparse.make_option("--printfetchseq", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, + optparse.make_option("--nopcsymbol", + action="callback", callback=noPCSymbol, + help="Disable PC symbols in trace output"), + optparse.make_option("--noprintcycle", + action="callback", callback=noPrintCycle, + help="Don't print cycle numbers in trace output"), + optparse.make_option("--noprintopclass", + action="callback", callback=noPrintOpclass, + help="Don't print op class type in trace output"), + optparse.make_option("--noprintthread", + action="callback", callback=noPrintThread, + help="Don't print thread number in trace output"), + optparse.make_option("--noprinteffaddr", + action="callback", callback=noPrintEA, + help="Don't print effective address in trace output"), + optparse.make_option("--noprintdata", + action="callback", callback=noPrintData, + help="Don't print result data in trace output"), + optparse.make_option("--printfetchseq", action="callback", callback=printFetchseq, help="Print fetch sequence numbers in trace output"), - optparse.make_option("--printcpseq", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, + optparse.make_option("--printcpseq", action="callback", callback=printCpseq, help="Print correct path sequence numbers in trace output"), - optparse.make_option("--dumponexit", type="choice", - choices=TrueOrFalse, - default="True", metavar=TorF, + optparse.make_option("--dumponexit", action="callback", callback=dumpOnExit, help="Dump trace buffer on exit"), optparse.make_option("--debugbreak", type="int", metavar="CYCLE", |