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-rw-r--r--src/arch/arm/tlb.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f30e195c1..2b50d4b28 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1418,6 +1418,11 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
Translation *translation, bool timing, bool functional,
bool is_secure, TLB::ArmTranslationType tranType)
{
+ // In a 2-stage system, the IPA->PA translation can be started via this
+ // call so make sure the miscRegs are correct.
+ if (isStage2) {
+ updateMiscReg(tc, tranType);
+ }
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);