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-rwxr-xr-xsrc/arch/isa_parser.py2
-rw-r--r--src/arch/sparc/miscregfile.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index b235398f1..6504c7b32 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1316,7 +1316,7 @@ class ControlRegOperand(Operand):
def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write control register as FP')
- wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name)
+ wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name)
wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name
return wb
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 8041e45c0..efaa22f67 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -470,7 +470,7 @@ Fault MiscRegFile::setRegWithEffect(int miscReg,
/** Floating Point Status Register */
case MISCREG_FSR:
- panic("Floating Point not implemented\n");
+ setReg(miscReg, val);
default:
#if FULL_SYSTEM
setFSRegWithEffect(miscReg, val, tc);