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AgeCommit message (Expand)Author
2014-05-09config: Bump DRAM sweep bus speed to match DDR4 configAndreas Hansson
2014-05-09tests: Reflect name change in DRAM testsAndreas Hansson
2014-05-09mem: Update DDR3 and DDR4 based on datasheetsAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Add precharge all (PREA) to the DRAM controllerAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Merge DRAM page-management calculationsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-04-17arm: Make sure UndefinedInstructions are properly initializedAli Saidi
2014-04-17arm: allow DC instructions by default so SE mode worksAli Saidi
2014-04-17sim, arm: implement more of the at variety syscallsAli Saidi
2014-05-09cpu: Useful getters for ActivityRecorderAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09cpu: Timebuf const accessorsAndrew Bardsley
2014-05-09arm: Add branch flags onto macroopsAndrew Bardsley
2014-05-09cpu: Allow setWhen on trace objectsAndrew Bardsley
2014-05-09arm: add preliminary ISA splits for ARM archCurtis Dunham
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
2014-05-09config: Avoid generating a reference to myself for Parent.anyGeoffrey Blake
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-05-09mem: Squash prefetch requests from downstream cachesMitch Hayenga
2014-05-09stats: Method stats sourceStephan Diestelhorst
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-05-09mem: Auto-generate CommMonitor trace file namesSascha Bischoff
2014-05-09arm: Panics in miscreg read functions can be tripped by O3 modelGeoffrey Blake
2014-05-09dev: Set HDLCD default pixel clock for 1080p @ 60HzChris Emmons
2014-05-09arm: quick hack to allow a greater number of CPUs to a guest OSMatt Evans
2014-05-09arm: Add Makefile for aarch64 build of util/m5Eric Van Hensbergen
2014-05-09arch: remove inline specifiers on all inst constrs, all ISAsCurtis Dunham
2014-05-09arm: cleanup ARM ISA definitionCurtis Dunham
2014-03-19ext: disable PLY debuggingCurtis Dunham
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
2014-04-23arm: Correctly display disassembly of vldmia/vstmiaCurtis Dunham
2014-04-23util: Valgrind suppression additionMitch Hayenga
2014-04-23sim: Use correct unit for abort messageAndreas Hansson
2014-04-23cpu: Fix setTranslateLatency() bug for squashed instructionsMitchell Hayenga
2014-04-23misc: Proper type check and import for PortRefSascha Bischoff
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-04-01mem: Don't print out the data of a cache blockMitch Hayenga
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
2014-04-23base: explicitly suggest potential use of 'All' debug flagsCurtis Dunham
2014-04-23arch: remove 'null update' check in isa-parserCurtis Dunham