gem5 - gem5

Age	Commit message (Expand)	Author
2012-04-28	Garnet: Correct computation of link utilization	Nilay Vaish
2012-04-26	util/regress: Add the missing comma in the list of builds	Nilay Vaish
2012-04-25	Regression: Add a test for x86 timing full system ruby simulation	Nilay Vaish
2012-04-25	Ruby: Remove extra statements from Sequencer	Nilay Vaish
2012-04-25	MEM: Use base class Master/SlavePort pointers in the bus	Andreas Hansson
2012-04-25	MEM: Add the PortId type and a corresponding id field to Port	Andreas Hansson
2012-04-25	clang/gcc: Use STL hash function for int64_t and uint64_t	Andreas Hansson
2012-04-24	X86: Update stats for the slightly changed TLB behavior.	Gabe Black
2012-04-24	X86: Clear out duplicate TLB entries when adding a new one.	Gabe Black
2012-04-23	ISA: Put parser generated files in a "generated" directory.	Gabe Black
2012-04-23	scons: update minimum SWIG version to 1.3.34	Steve Reinhardt
2012-04-22	base: Include cassert in trie.hh.	Gabe Black
2012-04-21	X86: Report an error if there's no kernel object, don't blindly use it.	Gabe Black
2012-04-17	SE Config: Changed se.py to support multithreaded mode	Jayneel Gandhi
2012-04-16	Config: Add command line options for disk image and memory size	Jayneel Gandhi
2012-04-15	CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.	Gabe Black
2012-04-15	X86: Fix a tiny typo in the load/store microop constructor.	Gabe Black
2012-04-14	X86: Use the AddrTrie class to implement the TLB.	Gabe Black
2012-04-14	sim: Update some comments in trie.hh that were meant to go in the last change.	Gabe Black
2012-04-14	sim: A trie data structure specifically to speed up paging lookups.	Gabe Black
2012-04-14	Ruby: Use MasterPort base-class pointers where possible	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-14	Regression: Add ANSI colours to highlight test status	Andreas Hansson
2012-04-14	clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6	Andreas Hansson
2012-04-13	SCons: restore Werror option in src/SConscript	Steve Reinhardt
2012-04-12	Stats: Update with use of std::map for ordered iteration in Ruby	Andreas Hansson
2012-04-12	Ruby: Ensure order-dependent iteration uses an ordered map	Andreas Hansson
2012-04-09	tests: Fix building unit tests.	Gabe Black
2012-04-06	rubytest: remove spurious printf	Brad Beckmann
2012-04-06	regress: ruby random tester and hammer stats updates	Brad Beckmann
2012-04-06	ruby: set SimpleTiming as the default cpu	Brad Beckmann
2012-04-06	slicc: Controllers attached to Sequencers no longer have to be named L1Cache.	Lisa Hsu
2012-04-06	sim-ruby: checkpointing fixes and dependent eventq improvements	Brad Beckmann
2012-04-06	slicc: fixed error message when the type has no inheritance	Brad Beckmann
2012-04-06	MOESI_hammer: tbe allocation and dependent wakeup fixes	Brad Beckmann
2012-04-06	python: added __nonzero__ function to SimObject Bool params	Brad Beckmann
2012-04-06	MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...	Brad Beckmann
2012-04-06	rubytest: seperated read and write ports.	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	NetworkTest: remove unnecessary memory allocation	Tushar Krishna
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-04-05	Ruby: Fix the example configurations option parsing	Andreas Hansson
2012-04-05	Python: Make the All proxy traverse SimObject children as well	Andreas Hansson
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-03-31	X86: Fix address size handling so real mode works properly.	Gabe Black
2012-03-30	MEM: Remove legacy DRAM in preparation for memory updates	Andreas Hansson
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-30	CPU: Unify initMemProxies across CPUs and simulation modes	Andreas Hansson