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AgeCommit message (Expand)Author
2011-04-15region: add a utility class for keeping track of regions of some rangeNathan Binkert
2011-04-15SortedDict: add functions for getting ranges of keys, values, itemsNathan Binkert
2011-04-15python: figure out if the m5.internal package exists even with demandimportNathan Binkert
2011-04-13refcnt: Update doxygen commentsNathan Binkert
2011-04-13refcnt: Inline comparison functionsNathan Binkert
2011-04-13main: separate out interact() so it can be used by other functionsNathan Binkert
2011-04-13util: fix the language type functionNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
2011-04-10ARM: Fix checkpoint restoration in ARM_SE.Ali Saidi
2011-04-10ARM: Get rid of some comments/todos that no longer apply.Ali Saidi
2011-04-06ruby: fixes to support more types of RubyRequestsBrad Beckmann
2011-04-04ARM: Update stats for default inclusion of CF adapter.Ali Saidi
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Fix bug in MicroLdrNeon templates for initiateAcc().Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-04-04ARM: Fix table walk going on while ASID changes errorAli Saidi
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Update stats for memory order violation checking patch.Ali Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-04-04IDE: Support x86, Alpha, and ARM use of the IDE controller.Ali Saidi
2011-04-04ARM: Fix checkpointing case where PL111 is powered off.Ali Saidi
2011-04-04ARM: Remove debugging warn that was accidently left in.Ali Saidi
2011-04-04ARM: Fix multiplication error in udelayAli Saidi
2011-04-01hammer: fixed dma uniproc errorBrad Beckmann
2011-03-31CacheMemory: add allocateVoid() that is == allocate() but no return value.Lisa Hsu
2011-03-31Ruby: Simplify SLICC and Entry/TBE handling.Lisa Hsu
2011-03-31Ruby: Add new object called WireBuffer to mimic a Wire.Lisa Hsu
2011-03-31Ruby: have the rubytester pass contextId to Ruby.Lisa Hsu
2011-03-31Ruby: enable multiple sequencers in one controller.Lisa Hsu
2011-03-31Ruby: pass Packet->Req->contextId() to Ruby.Lisa Hsu
2011-03-31Ruby: Bug in SLICC forgot semicolon at end of code.Lisa Hsu
2011-03-29sim: typecast Tick to UTick for eventQ assertKorey Sewell
2011-03-29Power: Fix compilation.Gabe Black
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-28Config: Import math in MI_example.pyNilay Vaish
2011-03-26tests: update reference outputs for ruby cache index changeSteve Reinhardt
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
2011-03-25ruby: fixed cache index settingBrad Beckmann
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-24Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.Gabe Black
2011-03-24Arm: Get rid of the unused copyStringArray32 method from Arm process classes.Gabe Black
2011-03-24ISA parser: Set up op_src_decl and op_dest_decl for pc operands.Gabe Black
2011-03-22This patch fixes a build error in networktest.cc that occurs with gcc4.2Tushar Krishna