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AgeCommit message (Expand)Author
2013-01-07arm: Fix draining of the pagetable walker when squashingAndreas Sandberg
2013-01-07cpu: Fix broken squashAfter implementation in O3 CPUAndreas Sandberg
2013-01-07o3 cpu: Remove unused variablesAndreas Sandberg
2013-01-07tests: Update the ignore regexps to reflect the M5->gem5 name changeAndreas Sandberg
2013-01-07sim: Remove unused variablesAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Remove unused params.hh header file in inorder CPUAndreas Sandberg
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Unify SimpleCPU and O3 CPU serialization codeAndreas Sandberg
2013-01-07cpu: Initialize the O3 pipeline from startup()Andreas Sandberg
2013-01-07cpu: Implement a flat register interface in thread contextsAndreas Sandberg
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07cpu: Check that the memory system is in the correct modeAndreas Sandberg
2013-01-07arch: Add support for invalidating TLBs when drainingAndreas Sandberg
2013-01-07mem: Remove the IIC replacement policyAndreas Sandberg
2013-01-07dev: Do not serialize timer parametersAndreas Hansson
2013-01-07scons: Enforce gcc >= 4.4 or clang >= 2.9 and c++0x supportAndreas Hansson
2013-01-07scons: Remove stale compiler optionsAndreas Hansson
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2013-01-07dev: Make the ethernet devices use a non-zero clockAndreas Hansson
2013-01-07scons: Whitelist useful environment variablesAndreas Sandberg
2013-01-07ARM: pl111/LCD framebuffer checkpointing fixChander Sudanthi
2013-01-07arch: Fix broken M5VarArgsFault initializationAndreas Sandberg
2013-01-07mem: Merge ranges that are part of the conf tableAndreas Hansson
2013-01-07base: Add support for merging of interleaved address rangesAndreas Hansson
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
2013-01-07config: Traverse lists when visiting children in all proxyAndreas Hansson
2013-01-07base: Simplify the AddrRangeMap by removing unused codeAndreas Hansson
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07mem: Tidy up bus addr range debug messagesAndreas Hansson
2013-01-07mem: Skip address mapper range checks to allow more flexibilityAndreas Hansson
2013-01-07base: Encapsulate the underlying fields in AddrRangeAndreas Hansson
2013-01-07mem: Remove the joining of neighbouring rangesAndreas Hansson
2013-01-07cpu: Share the send functionality between traffic generatorsAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07tests: Add support for skipping tests, skip EIO tests if not enabledAndreas Sandberg
2013-01-07cpu: Encapsulate traffic generator input in a streamAndreas Hansson
2013-01-07base: Add wrapped protobuf input streamAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2013-01-07base: Add wrapped protobuf output streamsAndreas Hansson
2013-01-07scons: Add support for google protobuf buildingAndreas Hansson
2013-01-07arm: Fix DMA event handling bug in the PL111 modelAndreas Sandberg
2013-01-07dev: Fix the Pl111 timings by separating pixel and DMA clockAndreas Hansson
2013-01-07stats: Update DRAM regression stats to match new configAndreas Hansson
2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
2013-01-07cpu: Fix the traffic gen read percentageAndreas Hansson
2013-01-07mem: Add sanity check to packet queue sizeAndreas Hansson
2013-01-07ruby: Fix missing cxx_header in SwitchAndreas Hansson
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