gem5 - gem5

Age	Commit message (Expand)	Author
2010-06-02	Simple CPU: Make the FloatRegs trace flag do something.	Gabe Black
2010-06-02	ARM: Fix up thumb decoding of coproc instructions.	Gabe Black
2010-06-02	ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR,...	Gabe Black
2010-06-02	CPU: Reset fetch offset after a exception	Ali Saidi
2010-06-02	ARM: Decode the VLDR instruction.	Gabe Black
2010-06-02	ARM: Implement the VLDR instruction.	Gabe Black
2010-06-02	ARM: Decode all the various forms of vmov.	Gabe Black
2010-06-02	ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.	Gabe Black
2010-06-02	ARM: Implement the various versions of VMOV.	Gabe Black
2010-06-02	ARM: Add a new RegImmOp base class.	Gabe Black
2010-06-02	ARM: Add a RegRegImmOp base class.	Gabe Black
2010-06-02	ARM: Widen the immediate fields in the misc instruction classes.	Gabe Black
2010-06-02	ARM: Add a function to decode VFP modified immediate constants.	Gabe Black
2010-06-02	ARM: Add a function to decode SIMD modified immediate constants.	Gabe Black
2010-06-02	ARM: Add fp operands to operands.isa.	Gabe Black
2010-06-02	ARM: Decode the VMRS instruction.	Gabe Black
2010-06-02	ARM: Update the set of FP related miscregs.	Gabe Black
2010-06-02	ARM: Implement the VMRS instruction.	Gabe Black
2010-06-02	ARM: Decode the VMSR instruction.	Gabe Black
2010-06-02	ARM: Implement the VMSR instruction.	Gabe Black
2010-06-02	ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) regis...	Gabe Black
2010-06-02	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	Gabe Black
2010-06-02	ARM: Implement the udiv instruction.	Gabe Black
2010-06-02	ARM: Implement the sdiv instruction.	Gabe Black
2010-06-02	ARM: Ignore writing a bad mode to CPSR with MSR.	Gabe Black
2010-06-02	ARM: Decode the CPS instruction.	Gabe Black
2010-06-02	ARM: Implement the CPS instruction.	Gabe Black
2010-06-02	ARM: Decode the SRS instruction.	Gabe Black
2010-06-02	ARM: Implement the SRS instruction.	Gabe Black
2010-06-02	ARM: Add a base class for SRS.	Gabe Black
2010-06-02	ARM: Implement a badMode function that says whether a mode is legal.	Gabe Black
2010-06-02	ARM: Allow flattening into any mode.	Gabe Black
2010-06-02	ARM: Decode TBB and TBH.	Gabe Black
2010-06-02	ARM: Decode the setend instruction.	Gabe Black
2010-06-02	ARM: Define the setend instruction.	Gabe Black
2010-06-02	ARM: Make a base class for instructions that use only an immediate.	Gabe Black
2010-06-02	ARM: Decode the arm version of ldrexd.	Gabe Black
2010-06-02	ARM: Decode the strex instructions.	Gabe Black
2010-06-02	ARM: Implement the strex instructions.	Gabe Black
2010-06-02	ARM: Set CPSR.E to SCTLR.EE on faults.	Gabe Black
2010-06-02	ARM: Warn about not implementing MPU translation, not panic about MMU.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	Gabe Black
2010-06-02	ARM: Allow access to the RGNR register.	Gabe Black
2010-06-02	ARM: Make the MPUIR register report that 1 unified data region is supported.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	Gabe Black
2010-06-02	ARM: Respect the E bit of the CPSR when doing loads and stores.	Gabe Black
2010-06-02	ARM: Zero the micropc when vectoring to a fault.	Gabe Black
2010-06-02	ARM: Implement the V7 version of alignment checking.	Gabe Black
2010-06-02	ARM: Decode the RFE instruction.	Gabe Black
2010-06-02	ARM: Implement the RFE instruction.	Gabe Black