gem5 - gem5

Age	Commit message (Expand)	Author
2018-06-25	syscall_emul: adding symlink system call	Matt Sinclair
2018-06-25	syscall_emul: adding link system call	Matt Sinclair
2018-06-22	mem-cache: Promote deferred targets on cache clean responses	Nikos Nikoleris
2018-06-22	mem-cache: Promote targets that don't require writable	Nikos Nikoleris
2018-06-22	mem-cache: Fix promoting of targets that need writable	Nikos Nikoleris
2018-06-22	mem-cache: Selectively clear downstream pending	Nikos Nikoleris
2018-06-22	SConstruct: additional message for the error checking of the python 2.7 headers	Matteo M. Fusi
2018-06-22	arch-arm: AArch32 execution triggering AArch64 SW Break	Giacomo Travaglini
2018-06-22	arch-arm: BadMode checking if corresponding EL is implemented	Giacomo Travaglini
2018-06-21	base: Add a class which encapsulates Fibers.	Gabe Black
2018-06-21	sim: Use the canonical way of iterating over a dictionary	Andreas Sandberg
2018-06-21	dev-arm: Use recurseDeviceTree instead of custom in platform	Andreas Sandberg
2018-06-21	cpu: Fix bug introduced by RequestPtr type change	Giacomo Travaglini
2018-06-20	base: Fix includes in AddrRangeMap header file	Nikos Nikoleris
2018-06-20	mem-cache: Fix TempCacheBlock insert	Jason Lowe-Power
2018-06-19	mem: Use address range to find the right physical address	Nikos Nikoleris
2018-06-19	mem: Use address range to find the destination port in the xbar	Nikos Nikoleris
2018-06-19	mem: Use the caching in the AddrRangeMap class in PhysicalMemory	Gabe Black
2018-06-19	mem: Use the caching built into AddrRangeMap in the xbar	Gabe Black
2018-06-19	base: Build caching into the AddrRangeMap class	Gabe Black
2018-06-19	base, mem: Disambiguate if an addr range is contained or overlaps	Nikos Nikoleris
2018-06-19	mem-cache: Fix support for secure blocks in the FALRU cache	Nikos Nikoleris
2018-06-15	mem-cache: Initialize CacheBlk data pointer	Daniel R. Carvalho
2018-06-15	mem-cache: Forward declare ReplaceableEntry	Daniel R. Carvalho
2018-06-15	dev-arm: Fix the address range for some I/O devices	Nikos Nikoleris
2018-06-15	tests,style: add RISC-V assembly tests	Tuan Ta
2018-06-15	sim: Add a SimObject python field which overrides the default c++ base.	Gabe Black
2018-06-14	cpu: Prevent suspended TimingSimple CPUs from fetching next instructions	Tuan Ta
2018-06-14	cpu: add a new instruction type 'Atomic'	Tuan Ta
2018-06-14	arch: support issuing Atomic Mem Operation (AMO) requests	Tuan Ta
2018-06-14	base,mem: Support AtomicOpFunctor in the classic memory system	Tuan Ta
2018-06-14	ruby: Revamp standalone SLICC script	Jason Lowe-Power
2018-06-14	arch-arm: Adapting IllegalExecution fault for AArch32	Giacomo Travaglini
2018-06-14	arch-arm: Add Illegal Execution flag to PCState	Giacomo Travaglini
2018-06-14	arch-arm: Read APSR in User Mode	Giacomo Travaglini
2018-06-14	system-arm: Split the VExpress_GEM5_V1 base dts	Andreas Sandberg
2018-06-14	dev-arm: Add new VExpress_GEM5_V1_Base Platform	Rohit Kurup
2018-06-14	cpu-minor: Remove redundant thread startup call	Andreas Sandberg
2018-06-14	dev-arm: Remove deprecated GIC test interfaces	Andreas Sandberg
2018-06-13	tests: Make "UnitTest"s more like GTest so they can be in other dirs.	Gabe Black
2018-06-13	mem-cache: Remove unnecessary cast in SectorTags::findVictim	Nikos Nikoleris
2018-06-13	arch-arm: Fix missing Request allocation	Giacomo Travaglini
2018-06-13	mem-cache: Insert on block allocation	Daniel R. Carvalho
2018-06-13	mem-cache: Make packet const in insertBlock	Daniel R. Carvalho
2018-06-13	mem-cache: Create Sector Cache	Daniel R. Carvalho
2018-06-12	tests: add some pthread and std::thread unit tests	Tuan Ta
2018-06-12	ruby: Fix initial weight in weighted LRU	Daniel R. Carvalho
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2018-06-11	misc: Substitute pointer to Request with aliased RequestPtr	Giacomo Travaglini
2018-06-08	mem-cache: Change Cache block tag check	Daniel R. Carvalho