gem5 - gem5

Age	Commit message (Expand)	Author
2011-05-23	config: reinstate implicit parenting on parameter assignment	Steve Reinhardt
2011-05-23	sim: add some DPRINTFs for debugging unserialization	Steve Reinhardt
2011-05-23	util/regress: make default action a more thorough regression	Steve Reinhardt
2011-05-23	configs: missed spot progress-interval change	Korey Sewell
2011-05-23	Stats: Update stats for minor O3 changes below.	Ali Saidi
2011-05-23	O3: Fix offset calculation into storeQueue buffer for store->load forwarding	Geoffrey Blake
2011-05-23	O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.	Geoffrey Blake
2011-05-23	O3: Fix issue with interrupts/faults occuring in the middle of a macro-op	Geoffrey Blake
2011-05-21	garnet: use vnet_type from protocol to decide buffer depths	Tushar Krishna
2011-05-21	configs: remove -p from ruby_network_test.py	Tushar Krishna
2011-05-20	configs: cleanup redundant/unused options	Korey Sewell
2011-05-20	slicc: added vnet_type to MI_example	Tushar Krishna
2011-05-18	gcc: fix an uninitialized variable warning from G++ 4.5	Nathan Binkert
2011-05-18	slicc: added vnet_type field to identify response vnets from others	Tushar Krishna
2011-05-18	garnet: rename and rearrange config parameters.	Tushar Krishna
2011-05-13	ARM: Fix up stats for previous changes to condition codes	Ali Saidi
2011-05-13	ARM: Generate condition code setting code based on which codes are set.	Ali Saidi
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-13	Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.	Chander Sudanthi
2011-05-13	ARM: Better RealView/Versatile EB platform support.	Chander Sudanthi
2011-05-13	O3: Fix an issue with a load & branch instruction and mem dep squashing	Geoffrey Blake
2011-05-12	stats: delete mysql support	Nathan Binkert
2011-05-12	stats: move code that loops over all stats into python	Nathan Binkert
2011-05-12	stats: better expose statistics to python.	Nathan Binkert
2011-05-09	work around gcc 4.5 warning	Nathan Binkert
2011-05-07	NetworkTest: added sim_cycles parameter to the network tester.	Tushar Krishna
2011-05-07	network: added Torus and Pt2Pt topologies	Tushar Krishna
2011-05-07	Trace: Remove the options trace-help and trace-flags	Nilay Vaish
2011-05-06	X86: Fix the Lldt instructions so they load the ldtr and not the tr.	Gabe Black
2011-05-05	ruby: use RubyMemory flag & remove setDebug() functionality	Korey Sewell
2011-05-04	ARM: Update ARM_FS stats for mp changes	Ali Saidi
2011-05-04	ARM: Configure bootloader parameters	Ali Saidi
2011-05-04	ARM: Add support for loading the a bootloader and configuring parameters for it	Ali Saidi
2011-05-04	ARM: Implement WFE/WFI/SEV semantics.	Prakash Ramrakhyani
2011-05-04	ARM: Add support for MP misc regs and broadcast flushes.	Ali Saidi
2011-05-04	ARM: Make GIC handle IPIs and multiple processors.	Prakash Ramrakhyani
2011-05-04	ARM: Add snoop control unit device.	Ali Saidi
2011-05-04	ARM: Add support for some more registers in the real view controller.	Ali Saidi
2011-05-04	ARM: Boot loader changes that make it more flexible about load and I/O addrs	Prakash Ramrakhyani
2011-05-04	O3/ARM: Update stats for recent changes.	Ali Saidi
2011-05-04	Debug: Add a function to cause the simulator to create a checkpoint from GDB.	Ali Saidi
2011-05-04	CPU: Add some useful debug message to the timing simple cpu.	Ali Saidi
2011-05-04	CPU: Fix a case where timing simple cpu faults can nest.	Ali Saidi
2011-05-04	O3: Remove assertion for case that is actually handled in code.	Ali Saidi
2011-05-04	Core: Add some documentation about the sim clocks.	Ali Saidi
2011-05-04	RealView: Fix the 24 and 100MHz clocks which were providing incorrect values.	Chris Emmons
2011-05-04	O3: Fix a small corner case with the lsq hazard detection logic.	Ali Saidi