gem5 - gem5

Age	Commit message (Expand)	Author
2010-06-02	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	Gabe Black
2010-06-02	ARM: Allow access to the RGNR register.	Gabe Black
2010-06-02	ARM: Make the MPUIR register report that 1 unified data region is supported.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	Gabe Black
2010-06-02	ARM: Respect the E bit of the CPSR when doing loads and stores.	Gabe Black
2010-06-02	ARM: Zero the micropc when vectoring to a fault.	Gabe Black
2010-06-02	ARM: Implement the V7 version of alignment checking.	Gabe Black
2010-06-02	ARM: Decode the RFE instruction.	Gabe Black
2010-06-02	ARM: Implement the RFE instruction.	Gabe Black
2010-06-02	ARM: Add a base class for the RFE instruction.	Gabe Black
2010-06-02	ARM: Make sure some undefined thumb32 instructions fault.	Gabe Black
2010-06-02	ARM: Squash the low order bits of the PC when performing a regular branch.	Gabe Black
2010-06-02	ARM: When changing the CPSR and branching, make sure the branch is second.	Gabe Black
2010-06-02	ARM: Ignore/warn when CSSELR or CCSIDR are accessed.	Gabe Black
2010-06-02	ARM: Ignore/warn access to the bpimva registers.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the dccmvac register.	Gabe Black
2010-06-02	ARM: Decode the enterx and leavex instructions.	Gabe Black
2010-06-02	ARM: Implement the enterx and leavex instructions.	Gabe Black
2010-06-02	ARM: Fix the implementation of BX to work in thumbEE mode.	Gabe Black
2010-06-02	ARM: When an instruction is intentionally undefined, fault on it.	Gabe Black
2010-06-02	ARM: Decode the thumb version of the ldrd and strd instructions.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Decode the thumb32 load byte/memory hint instructions.	Gabe Black
2010-06-02	ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to icimvau.	Gabe Black
2010-06-02	ARM: Ignore/warn on iciallu.	Gabe Black
2010-06-02	ARM: Ignore/warn on ICIALLUIS.	Gabe Black
2010-06-02	ARM: Add support for the clidr register.	Gabe Black
2010-06-02	ARM: Decode the unimplemented data barrier CP15 accesses.	Gabe Black
2010-06-02	ARM: Implement a stub of CPACR.	Gabe Black
2010-06-02	ARM: Actually write the value of sctlr in ISA.clear().	Gabe Black
2010-06-02	ARM: Replace the ARM decode of CP15 MCR and MRC instructions.	Gabe Black
2010-06-02	ARM: Decode the unimplemented cp15 instruction barrier.	Gabe Black
2010-06-02	ARM: Ignore accesses to DCCIMVAC.	Gabe Black
2010-06-02	ARM: Allow accesses to the software thread id registers.	Gabe Black
2010-06-02	ARM: Allow accesses to the contextidr register.	Gabe Black
2010-06-02	ARM: Warn about and ignore accesses to DCCISW.	Gabe Black
2010-06-02	ARM: Decode the thumb versions of the mcr and mrc instructions.	Gabe Black
2010-06-02	ARM: Implement the mrc and mcr instructions.	Gabe Black
2010-06-02	ARM: Rename the RevOp base class to something more generic.	Gabe Black
2010-06-02	ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.	Gabe Black
2010-06-02	ARM: Implement a function to decode CP15 registers to MiscReg indices.	Gabe Black
2010-06-02	ARM: Decode the bfi and bfc instructions.	Gabe Black
2010-06-02	ARM: Implement the bfc and bfi instructions.	Gabe Black
2010-06-02	ARM: Decode the ubfx and sbfx instructions.	Gabe Black
2010-06-02	ARM: Decode miscellaneous arm mode media instructions.	Gabe Black
2010-06-02	ARM: Implement the ubfx and sbfx instructions.	Gabe Black
2010-06-02	ARM: Add a register, immediate, immediate to register base for [su]bfx.	Gabe Black
2010-06-02	ARM: Decode the clz instruction.	Gabe Black
2010-06-02	ARM: Implement the clz instruction.	Gabe Black