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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
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Age
Commit message (
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Author
2006-12-19
fix twinx loads a little bit
Ali Saidi
2006-12-18
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Ali Saidi
2006-12-17
Nate's utility for compiling m5
Nathan Binkert
2006-12-17
Utilities for doing a format check for some elements of proper
Nathan Binkert
2006-12-17
Compilation fixes.
Gabe Black
2006-12-17
Added in the extended twin load format
Gabe Black
2006-12-16
Merge zizzer:/bk/newmem
Gabe Black
2006-12-16
Merge zizzer:/bk/sparcfs/
Gabe Black
2006-12-16
Support for twin loads.
Gabe Black
2006-12-16
Compiler error fix.
Gabe Black
2006-12-15
Merge zizzer:/bk/newmem
Lisa Hsu
2006-12-15
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-15
small change to eliminate address range overlap.
Lisa Hsu
2006-12-15
little fixes i noticed while searching for reason for address range issues (b...
Lisa Hsu
2006-12-15
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-15
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-15
some small general fixes to make everythign work nicely with other ISAs, now ...
Lisa Hsu
2006-12-15
loadstore.isa:
Lisa Hsu
2006-12-15
tlb.cc:
Lisa Hsu
2006-12-15
Use my range_map to speed up findPort() in the bus. The snoop code could stil...
Ali Saidi
2006-12-15
Optimized the TLB translations with some caching
Ali Saidi
2006-12-14
flesh out twinx asis
Ali Saidi
2006-12-13
Split CachePort class into CpuSidePort and MemSidePort
Steve Reinhardt
2006-12-13
Merge zizzer:/bk/newmem
Lisa Hsu
2006-12-13
fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
Lisa Hsu
2006-12-13
Merge zizzer:/bk/newmem
Lisa Hsu
2006-12-13
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-12
Merge zizzer:/bk/newmem
Lisa Hsu
2006-12-12
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-12-12
Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Ali Saidi
2006-12-12
Allow for multiple redirects to happen on a single cycle (only the one for th...
Kevin Lim
2006-12-12
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(In...
Steve Reinhardt
2006-12-12
If no tests are specified for regression, just build the binaries
Steve Reinhardt
2006-12-12
Get rid of unused lock code.
Steve Reinhardt
2006-12-11
Fix up in case a req hasn't yet been generated for this instruction (if there...
Kevin Lim
2006-12-11
Fix for fetch to use the icache's block size to generate proper access size.
Kevin Lim
2006-12-10
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
Steve Reinhardt
2006-12-10
Reorder CacheTags members for better cache performance.
Steve Reinhardt
2006-12-10
Get rid of dummy 'hello world' outputs.
Steve Reinhardt
2006-12-10
Delete parser reference outputs so that test will no longer be run.
Steve Reinhardt
2006-12-10
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
Steve Reinhardt
2006-12-10
Add '-j' option directly to regress script (passed to scons).
Steve Reinhardt
2006-12-09
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2006-12-09
fix lisa's hand merge
Ali Saidi
2006-12-09
Merge zizzer:/bk/sparcfs
Ali Saidi
2006-12-09
Allocate the correct number of global registers
Ali Saidi
2006-12-08
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-08
mostly implemented SOFTINT relevant interrupt stuff.
Lisa Hsu
2006-12-07
get legion/m5 to first tlb miss fault
Ali Saidi
2006-12-07
Change detault regression build from opt to fast.
Steve Reinhardt
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