gem5 - gem5

Age	Commit message (Expand)	Author
2012-10-25	arm: Don't export private GIC methods	Andreas Sandberg
2012-10-25	arm: Create a GIC base class and make the PL390 derive from it	Andreas Sandberg
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-02-15	cpu: Refactor memory system checks	Andreas Sandberg
2013-02-15	config: Remove O3 dependencies	Andreas Sandberg
2013-02-15	config: Move CPU handover logic to m5.switchCpus()	Andreas Sandberg
2013-02-15	config: Cleanup CPU configuration	Andreas Sandberg
2013-02-15	cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy	Andreas Sandberg
2013-02-15	cpu: Add CPU metadata om the Python classes	Andreas Sandberg
2013-02-15	arm: fix some fp comparisons that worked by accident.	Ali Saidi
2013-02-15	cpu: include set in o3/commit_impl.	Ali Saidi
2013-02-15	ARM: Fix an issue with clang generating wrong code.	Ali Saidi
2013-02-15	cpu: fix case with o3 cpu blocking and unblocking decode in cycle	Ali Saidi
2013-02-15	cpu: Fix a livelock in the o3 cpu.	Ali Saidi
2013-02-10	base: Add support for newer versions of IPython	Andreas Sandberg
2013-02-14	Ruby: Fix compilation errors on gcc 4.7 and clang 3.2	Andreas Hansson
2013-02-10	regressions: update stats due to changes to ruby	Nilay Vaish
2013-02-10	ruby: MI protocol: add a missing transition	Nilay Vaish
2013-02-10	ruby: enable multiple clock domains	Nilay Vaish
2013-02-10	ruby: replace Time with Cycles (final patch in the series)	Nilay Vaish
2013-02-10	ruby: replace Time with Cycles in garnet fixed and flexible	Nilay Vaish
2013-02-10	ruby: replace Time with Tick in replacement policy classes	Nilay Vaish
2013-02-10	ruby: convert block size, memory size to unsigned	Nilay Vaish
2013-02-10	ruby: replace Time with Cycles in MessageBuffer	Nilay Vaish
2013-02-10	ruby: replace Time with Cycles in Memory Controller	Nilay Vaish
2013-02-10	ruby: Replace Time with Cycles in SequencerMessage	Nilay Vaish
2013-02-10	ruby: replace Time with Cycles in Message class	Nilay Vaish
2013-02-10	ruby: replaces Time with Cycles in many places	Nilay Vaish
2013-02-10	base: add some mathematical operators to Cycles class	Nilay Vaish
2013-02-10	ruby: modifies histogram add() function	Nilay Vaish
2013-02-10	ruby: record fully busy cycle with in the controller	Nilay Vaish
2013-02-10	base: Fix broken IPython argument handling	Andreas Sandberg
2013-02-10	config: Don't call sys.exit in interactive mode in run()	Andreas Sandberg
2013-01-31	sim: remove unused struct priority_compare	Nilay Vaish
2013-01-31	ruby: correct computation of number of bits required for address	Nilay Vaish
2013-01-31	mem: Add comments for the DRAM address decoding	Andreas Hansson
2013-01-31	stats: Update stats for regressions using SimpleDDR3	Andreas Hansson
2013-01-31	mem: Add DDR3 and LPDDR2 DRAM controller configurations	Andreas Hansson
2013-01-31	mem: Add tTAW and tFAW to the SimpleDRAM model	Ani Udipi
2013-01-31	mem: Separate out the different cases for DRAM bus busy time	Andreas Hansson
2013-01-28	cache: remove drainManager because it's not used	Anthony Gutierrez
2013-01-28	merged 798c2cec8e37 and e96ff45795bc	Nilay Vaish
2013-01-28	stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3	Andreas Hansson
2013-01-28	ruby: remove get_time()	Nilay Vaish
2013-01-28	ruby: remove call to curCycle in panic()	Nilay Vaish
2013-01-24	regressions: update stats due to branch predictor changes	Nilay Vaish
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-22	o3 cpu: fix zero reg problem	Andrea Pellegrini
2013-01-22	x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch	Nilay Vaish
2013-01-21	scons: Disable protobuf if pkg-config and CheckLib fails	Andreas Hansson