gem5 - gem5

Age	Commit message (Expand)	Author
2012-02-24	Ruby: Simplify tester ports by not using SimpleTimingPort	Andreas Hansson
2012-02-24	MEM: Move all read/write blob functions from Port to PortProxy	Andreas Hansson
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-24	MEM: Fatal when no port can be found for an address	Andreas Hansson
2012-02-20	SimObject: make get_config_as_dict() tolerate undefined params	Steve Reinhardt
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	bp: fix up stats for changes to branch predictor	Ali Saidi
2012-02-13	BPred: Fix RAS to handle predicated call/return instructions.	Mrinmoy Ghosh
2012-02-13	BP: Fix several Branch Predictor issues.	Mrinmoy Ghosh
2012-02-13	MEM: Explicit ports and Python binding on CopyEngine	Andreas Hansson
2012-02-13	MEM: Pass the ports from Python to C++ using the Swig params	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	tests: fix diff-out script for op/inst stat changes.	Ali Saidi
2012-02-12	X86: open flags: Another patch from Vince Weaver	Gabe Black
2012-02-12	configs: fix minor config bugs posted on the mailing list	Ali Saidi
2012-02-12	stats: update stats for insts/ops and master id changes	Ali Saidi
2012-02-12	cpu: add separate stats for insts/ops both globally and per cpu model	Anthony Gutierrez
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-02-12	Regressions: Update stats due to change in MESI protocol	Nilay Vaish
2012-02-11	SPARC: Make PSTATE and HPSTATE a BitUnion.	Gabe Black
2012-02-10	Ruby: Remove isTagPresent() calls from Sequencer.cc	Nilay Vaish
2012-02-10	MESI: Add queues for stalled requests	Nilay Vaish
2012-02-10	sim/system: initialize the pagePtr variable	Nilay Vaish
2012-02-10	Regressions: Update stats due to O3 CPU changes	Nilay Vaish
2012-02-10	O3 CPU: Improve handling of delayed commit flag	Nilay Vaish
2012-02-10	O3 CPU: Strengthen condition for handling interrupts	Nilay Vaish
2012-02-10	O3 CPU: Provide the squashing instruction	Nilay Vaish
2012-02-10	O3 Fetch: Check if PC is pointing to Microcode ROM	Nilay Vaish
2012-02-10	SE/FS: Record the system pointer all the time for the simple CPU.	Gabe Black
2012-02-09	MEM: Remove onRetryList from BusPort and rely on retryList	Andreas Hansson
2012-02-07	Checker: Access workload element 0 only if there is an element 0.	Gabe Black
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-02-07	m5=>gem5: Make the regression script build gem5.* instead of m5.*	Gabe Black
2012-02-05	X86: Rename the bridge which allows commnication back to the local APICs.	Gabe Black
2012-02-05	Regressions: Fix the regress script when "all" is used.	Gabe Black
2012-02-03	System: Forgot to qrefresh with my last change.	Gabe Black
2012-02-02	System: Fix the check which detects running out of physical memory.	Gabe Black
2012-02-02	Regression: Update the regress script after SE/FS merge	Andreas Hansson
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	MEM: Remove the otherPort from the cache ports	Andreas Hansson
2012-01-31	Thread: Use inherited baseCpu rather than cpu in SimpleThread	Andreas Hansson
2012-01-31	util: implements "writefile" gem5 op to export file from guest to host filesy...	Dam Sunwoo