summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2012-09-27Configs: Fix memtest.py by moving the system portAndreas Hansson
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25ARM: added support for flattened device tree blobsDam Sunwoo
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25mem: Add a gasket that allows memory ranges to be re-mapped.Ali Saidi
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25Util: Added script to semantically diff two config.ini filesSascha Bischoff
2012-09-25arm: Use a static_assert to test that miscRegName[] is completeAndreas Sandberg
2012-09-25base: Check for static_assert support and provide fallbackAndreas Sandberg
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-09-25gem5: Update the README file to be a bit less out-of-date.Ali Saidi
2012-09-25build: Add missing dependencies when building param SWIG interfacesAndreas Sandberg
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
2012-09-23RubyPort and Sequencer: Fix drainingJoel Hestness
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-21Scons: Verbose messages when dependencies are not installedAndreas Hansson
2012-09-21SE: Ignore FUTEX_PRIVATE_FLAG of sys_futexLluc Alvarez
2012-09-20bus: removed outdated warn regarding 64 B block sizesAnthony Gutierrez
2012-09-19Mem: Remove the file parameter from AbstractMemoryAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify Range by removing stream input/outputAndreas Hansson
2012-09-19AddrRange: Remove unused range_multimapAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-18ruby: eliminate typedef integer_tNilay Vaish
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
2012-09-18Mem: Add a maximum bandwidth to SimpleMemoryAndreas Hansson
2012-09-14gcc: Enable Link-Time Optimization for gcc >= 4.6Andreas Hansson
2012-09-14scons: Add a target for google-perftools profilingAndreas Hansson
2012-09-14scons: Restructure ccflags and ldflagsAndreas Hansson
2012-09-14scons: Use c++0x with gcc >= 4.4 instead of 4.6Andreas Hansson
2012-09-13Stats: Remove the reference stats that are no longer presentAndreas Hansson
2012-09-12se.py Ruby: Connect TLB walker portsJoel Hestness
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 06:18:00 +0000