summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2006-10-29An attempt to serialize the state of the micro code mechanism in the simple cpu.Gabe Black
2006-10-29Move the mem classes into util.isa so that multiple inheritance can be used i...Gabe Black
2006-10-29Fix when the IsDelayedCommit flag is set.Gabe Black
2006-10-29Bring casa and casxa up to dateGabe Black
2006-10-29Fixed ldstub to use the right format, and made the load/store operations use ...Gabe Black
2006-10-29Add an integer microcode register.Gabe Black
2006-10-28Merge zizzer:/bk/newmemAli Saidi
2006-10-28remove intel nic from SConscriptAli Saidi
2006-10-28This one really needs to be arch/faults.hhGabe Black
2006-10-28Include the right version of faults.hhGabe Black
2006-10-28Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-28One last adjustment to get rid of skew in the simple atomic cpu.Gabe Black
2006-10-27Merge zizzer:/bk/newmemLisa Hsu
2006-10-27factor out common run code from se.py and fs.py.Lisa Hsu
2006-10-27Merge zizzer:/bk/newmemAli Saidi
2006-10-27add packet_access.hhAli Saidi
2006-10-27A more complete attempt to fix the clock skew.Gabe Black
2006-10-27Potential fix to clock skew problem.Gabe Black
2006-10-27Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-27Update stats for fill/spill handlersGabe Black
2006-10-27Got rid of some outdated comments.Gabe Black
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
2006-10-27Clean up MiscRegFileGabe Black
2006-10-26Reorganized the MiscRegFileGabe Black
2006-10-26Cleaned up the decoder slightly.Gabe Black
2006-10-26Added a few functions to stuff values into bitfields in an instruction.Gabe Black
2006-10-26Changed the number of register windows to be more realistic.Gabe Black
2006-10-26Got rid of some debug outputGabe Black
2006-10-26Change the default function from setMiscRegWithEffect to setMiscRegGabe Black
2006-10-26Merge zizzer:/bk/newmemLisa Hsu
2006-10-26se.py:Lisa Hsu
2006-10-26Merge zizzer:/bk/newmemAli Saidi
2006-10-25Fix simple timing port keep a list of all packets, have only one event, and s...Ali Saidi
2006-10-25Fixed the priv instruction format.Gabe Black
2006-10-25Implemented the saved and restored instructions, fixed up register window ins...Gabe Black
2006-10-25Fixed the bitfield FCN to include the right bits.Gabe Black
2006-10-25Implemented the SPARC fill and spill handlers.Gabe Black
2006-10-25Fix fixPacket functionality to calculate sizes properlyRon Dreslinski
2006-10-24Replace the Alpha No op with a SPARC one.Gabe Black
2006-10-24Fix fs.py. Lisa did you test this? Is there some wierd python version thing?Ali Saidi
2006-10-24Merge zizzer:/bk/newmemAli Saidi
2006-10-24Add more traceflags for ethernetAli Saidi
2006-10-24Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-10-23warmup of 1B cpu cycles.Lisa Hsu
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
2006-10-23get rid of the "resume" step at the end of changeToTiming/Atomic because this...Lisa Hsu
2006-10-23make this parallel to the other cpu types so that resume works correctly.Lisa Hsu
2006-10-23make a lot of the same changes as to fs.py for checkpointing.Lisa Hsu
2006-10-23changes regarding fs.pyLisa Hsu
2006-10-23Minor compile fix. Not sure why this is broken.Gabe Black
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 19:10:41 +0000