gem5 - gem5

Age	Commit message (Expand)	Author
2012-06-05	all: Update stats for memory per master and total fix.	Ali Saidi
2012-06-05	stats: when applying an operation to two vectors sum the components first.	William Wang
2012-06-05	Mem: add per-master stats to physmem	Dam Sunwoo
2012-06-05	ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT	Geoffrey Blake
2012-06-05	ARM: removed extra white space	Chander Sudanthi
2012-06-05	ARM: Fix MPIDR and MIDR register implementation.	Chander Sudanthi
2012-06-05	ARM: PS2 encoding fix	Chander Sudanthi
2012-06-05	sim: Provide a framework for detecting out of data checkpoints and migrating ...	Ali Saidi
2012-06-05	stats: Add stats unittest for total calculations.	Ali Saidi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Add support for tcmalloc if it's installed and available.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-05	ARM: Fix over-eager assert in gic.	Ali Saidi
2012-06-05	stats: Provide a mechanism to get a callback when stats are dumped.	Mitchell Hayenga
2012-06-05	ARM: Fix compilation on ARM after Gabe's change.	Ali Saidi
2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
2012-06-04	X86: Update stats for the CPUID change.	Gabe Black
2012-06-04	X86: Ensure that the CPUID instruction always writes its outputs.	Gabe Black
2012-06-04	X86: Ensure that the decoder's internal ExtMachInst is completely initialized.	Gabe Black
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-09	Stats: Fix stats to match output after changeset 8800b05e1cb3	Andreas Hansson
2012-05-30	gcc: Small fixes to compile with gcc 4.7	Andreas Hansson
2012-05-30	Bus: Remove redundant packet parameter from isOccupied	Andreas Hansson
2012-05-30	Bus: Turn the PortId into a transport function parameter	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-30	Packet: Updated comments for src and dest fields	Andreas Hansson
2012-05-30	Bridge: Split deferred request, response and sender state	Andreas Hansson
2012-05-28	X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.	Gabe Black
2012-05-27	X86: Add a 32 bit hello world test binary.	Gabe Black
2012-05-27	X86: Move the GDT down to where it can be accessed in 32 bit mode.	Gabe Black
2012-05-27	X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.	Gabe Black
2012-05-26	ISA,CPU: Generalize and split out the components of the decode cache.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-05-25	CPU: Simplify the implementation of the decode cache.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson
2012-05-23	Packet: Cleaning up packet command and attribute	Andreas Hansson
2012-05-23	Config: Use the attribute naming and include ports in JSON	Andreas Hansson
2012-05-23	DMA: Split the DMA device and IO device into seperate files	Andreas Hansson
2012-05-23	MEM: Add a snooping DMA port subclass for table walker	Andreas Hansson
2012-05-23	Config: Exit with fatal if a port is already connected	Andreas Hansson
2012-05-22	X86 Regression: update stats due to cc register split	Nilay Vaish
2012-05-22	Ruby: Remove the unused src/mem/ruby/common/Driver.* files.	Nilay Vaish
2012-05-22	Ruby Sequencer: Schedule deadlock check event at correct time	Nilay Vaish
2012-05-22	X86: Split Condition Code register	Nilay Vaish
2012-05-19	x86 ISA: Implement the sse3 haddps instruction.	Marc Orr
2012-05-19	Syscalls: warn when the length argument to mmap is excessive.	Gabe Black
2012-05-14	Mem: Fix size check when allocating physical memory	Lena Olson
2012-05-16	Config: Fix a typo in the se.py script for setting fastmem	Andreas Hansson