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AgeCommit message (Expand)Author
2013-08-20ruby: add option for number of transitions per cycleNilay Vaish
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
2013-08-20base: Fix VectorPrint initialisationAndreas Hansson
2013-08-19stats: Cumulative stats updateAndreas Hansson
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19cpu: Fix TrafficGen trace playbackSascha Bischoff
2013-08-19mem: Use STL deque in favour of list for DRAM queuesAndreas Hansson
2013-08-19mem: Perform write merging in the DRAM write queueAndreas Hansson
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
2013-08-19alpha: Check interrupts before quiesceAndreas Hansson
2013-08-19stats: Fix issue when printing 2D vectorsSascha Bischoff
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
2013-08-19mem: Warn instead of panic for tXAW violationAndreas Hansson
2013-08-19mem: Allow disabling of tXAW through a 0 activation limitAndreas Hansson
2013-08-19mem: Add an internal packet queue in SimpleMemoryAndreas Hansson
2013-08-19cpu: Fix a bug in the O3 CPU introduced by the cache line patchAndreas Hansson
2013-08-14arm: use -march when compiling m5op_arm.SAnthony Gutierrez
2013-08-07ruby: slicc: remove double trigger, continueProcessingNilay Vaish
2013-08-07ruby: slicc: move some code to AbstractControllerNilay Vaish
2013-08-07x86: add tlb checkpointingNilay Vaish
2013-07-19cpu: Remove unused getBranchPred() method from BaseCPUAndreas Sandberg
2013-07-18Configs: Fix up maxtick and maxtimeJoel Hestness
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
2013-07-18scons: Use python-config instead of distutilsAndreas Hansson
2013-07-18sim: Make MaxTick in Python match the one in C++Andreas Hansson
2013-07-15loader: Load weak symbols for function tracingDeyuan Guo
2013-07-15debug : Fixes the issue wherein Debug symbols were not getting dumped into tr...Umesh Bhaskar
2013-07-11dev: make BasicPioDevice take size in constructorSteve Reinhardt
2013-07-11dev: consistently end device classes in 'Device'Steve Reinhardt
2013-07-11dev/arm: get rid of AmbaDev namespaceSteve Reinhardt
2013-07-11devices: make more classes derive from BasicPioDeviceSteve Reinhardt
2013-07-11ruby: removed the very old double trigger hackBrad Beckmann
2013-07-02regressions: update a couple stats.txtNilay Vaish
2013-07-02regressions: update a couple of configsNilay Vaish
2013-06-28ruby: append transition comment only when in opt/debugNilay Vaish
2013-06-28configs: rearrange the available options in Options.pyNilay Vaish
2013-06-28ruby: network: remove reconfiguration codeNilay Vaish
2013-06-28ruby: check for compatibility between mem size and num dirsNilay Vaish
2013-06-27stats: Update stats for monitor, cache and bus changesAndreas Hansson
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a BaseSESystem builder for re-use in regressionsAndreas Hansson
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