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Author
2012-07-11
x86: added page size in bytes tlb entry function
Brad Beckmann
2012-07-11
ruby: improved DRAM reset comment
Brad Beckmann
2012-07-10
regress: ruby stat additions and config changes
Brad Beckmann
2012-07-10
syscall emulation: Add the futex system call.
Marc Orr
2012-07-10
x86: logSize and lruSeq are now optional ckpt params
Brad Beckmann
2012-07-10
Add hook to call map() on Process from python.
Steve Reinhardt
2012-07-10
# User Brad Beckmann <Brad.Beckmann@amd.com>
Brad Beckmann
2012-07-10
ruby: remove the cpu assumptions for the random tester
Brad Beckmann
2012-07-10
# User Brad Beckmann <Brad.Beckmann@amd.com>
Brad Beckmann
2012-07-10
imported patch jason/slicc-external-structure-fix
Brad Beckmann
2012-07-10
ruby: banked cache array resource model
Brad Beckmann
2012-07-10
ruby: tag and data cache access support
Joel Hestness
2012-07-10
ruby: adds reset function to Ruby memory controllers
Nuwan Jayasena
2012-07-10
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Nuwan Jayasena
2012-07-10
cpu: added assertions to ensure the correct proxies are used
Brad Beckmann
2012-07-10
ruby: changes how Topologies are created
Brad Beckmann
2012-07-09
EventManager: Rename queue accessor and remove cast operator
Andreas Hansson
2012-07-09
Mem: Make members relating to range and size constant
Andreas Hansson
2012-07-09
Port: Hide the queue implementation in SimpleTimingPort
Andreas Hansson
2012-07-09
Stats: Updates due to bus changes
Andreas Hansson
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-07-09
Bus: Make the default bus width 8 bytes instead of 64
Andreas Hansson
2012-07-09
Bus: Split the bus into separate request/response layers
Andreas Hansson
2012-07-09
Bus: Add a notion of layers to the buses
Andreas Hansson
2012-07-09
Bus: Replace tickNextIdle and inRetry with a state variable
Andreas Hansson
2012-07-09
Port: Make getAddrRanges const
Andreas Hansson
2012-07-09
Port: Add getAddrRanges to master port (asking slave port)
Andreas Hansson
2012-07-09
Port: Add isSnooping to slave port (asking master port)
Andreas Hansson
2012-07-09
Port: Move retry from port base class to Master/SlavePort
Andreas Hansson
2012-07-09
Fix: Address a few benign memory leaks
Andreas Hansson
2012-07-02
gcc: Fix warnings for gcc 4.7 and clang 3.1
Andreas Hansson
2012-06-29
Cache: Fix the LRU policy for classic memory hierarchy
Lena Olson
2012-06-29
Bus: enable non/coherent buses sub-classes
Uri Wiener
2012-06-29
Mem: fix master id assertion in cache_impl.hh
Dam Sunwoo
2012-06-29
Style: Make style.py's invalid warning print which file caused the infraction.
Matt Evans
2012-06-29
Mem: Fix a livelock resulting in LLSC/locked memory access implementation.
Matt Evans
2012-06-29
Stats: Update stats for RAS and LRU fixes.
Ali Saidi
2012-06-29
O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.
Nathanael Premillieu
2012-06-29
ARM: Fix identification of one RAS pop instruction.
Ali Saidi
2012-06-29
Cache: Only invalidate a line in the cache when an uncacheable write is seen.
Ali Saidi
2012-06-29
ARM: Update version of linux we claim to be to 3.0.0.
Ali Saidi
2012-06-29
ARM: Fix issue with predicted next pc being wrong because of advance() ordering.
Ali Saidi
2012-06-27
ARM: Fix address range issue with VExpress EMM
Ali Saidi
2012-06-20
swig: Use SWIG from environment when determining version
Andreas Hansson
2012-06-18
Build: Point to the appropriate tcmalloc package
Andreas Hansson
2012-06-11
configs: add run scripts for ics/gb versions of android and bbench
Anthony Gutierrez
2012-06-11
ARM: implement the ProcessInfo methods
Anthony Gutierrez
2012-06-11
scons: Make compiler version error more verbose and easier to debug.
Ali Saidi
2012-06-11
Regression: Fix some bugs in simple-timing-mp-ruby.py.
Marc Orr
2012-06-08
Timing CPU: Remove a redundant port pointer
Andreas Hansson
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