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Author
2012-11-02
Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Andreas Sandberg
2012-10-31
mem: Fix typo in port comments
Andreas Hansson
2012-10-31
stats: Update stats for fixed simple-atomic-mp config
Andreas Hansson
2012-10-31
config: Fix a typo in the simple-atomic-mp configuration
Andreas Hansson
2012-10-30
stats: Update stats for unified cache configuration
Andreas Hansson
2012-10-30
config: Unify caches used in regressions and adjust L2 MSHRs
Andreas Hansson
2012-10-27
regressions: update stats for ruby fs test
Nilay Vaish
2012-10-27
ruby: set the is_icache param for caches
Malek Musleh
2012-10-27
Ruby: Use block size in configuring directory bits in address
Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26
config: Add a check for fastmem only used with Atomic CPU
Andreas Hansson
2012-10-26
config: Remove unused mem_size in fs.py
Andreas Hansson
2012-10-26
config: Fix the cache class naming in regression scripts
Andreas Hansson
2012-10-25
stats: Update the stats to reflect the 1GHz default system clock
Andreas Hansson
2012-10-25
dev: Make default clock more reasonable for system and devices
Andreas Hansson
2012-10-25
stats: Update stats to reflect use of SimpleDRAM
Andreas Hansson
2012-10-25
config: Use SimpleDRAM in full-system, and with o3 and inorder
Andreas Hansson
2012-10-25
config: Use shared cache config for regressions
Andreas Hansson
2012-10-25
arm: Use table walker clock that is inherited from CPU
Andreas Hansson
2012-10-23
stats: Update stats for DMA port send
Andreas Hansson
2012-10-23
dev: Remove zero-time loop in DMA timing send
Andreas Hansson
2012-10-23
stats: Update t1000 stats to match recent changes
Andreas Hansson
2012-10-18
ruby: functional access updates to network test protocol
Nilay Vaish
2012-10-16
regressions: update stats for eio tests
Nilay Vaish
2012-10-15
regressions: update stats due to change to ruby memory system
Nilay Vaish
2012-10-15
ruby: improved support for functional accesses
Nilay Vaish
2012-10-15
memtest: move check on outstanding requests
Nilay Vaish
2012-10-15
ruby: register multiple memory controllers
Nilay Vaish
2012-10-15
ruby: remove AbstractMemOrCache
Nilay Vaish
2012-10-15
ruby: allow function definition in slicc structs
Nilay Vaish
2012-10-15
ruby banked array: do away with event scheduling
Nilay Vaish
2012-10-15
ruby: reset timing after cache warm up
Nilay Vaish
2012-10-15
Mem: Fix incorrect logic in bus blocksize check
Andreas Hansson
2012-10-15
Port: Add protocol-agnostic ports in the port hierarchy
Andreas Hansson
2012-10-15
Mem: Separate the host and guest views of memory backing store
Andreas Hansson
2012-10-15
Checkpoint: Make system serialize call children
Andreas Hansson
2012-10-15
Mem: Use deque instead of list for bus retries
Andreas Hansson
2012-10-15
Fix: Address a few minor issues identified by cppcheck
Andreas Hansson
2012-10-15
Stats: Update stats for cache timings in cycles
Andreas Hansson
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-10-15
Stats: Update memtest stats after setting clock
Andreas Hansson
2012-10-15
Configs: Set the memtest clock to a reasonable value
Andreas Hansson
2012-10-15
Stats: Update stats for new default L1-to-L2 bus clock and width
Andreas Hansson
2012-10-15
Regression: Use CPU clock and 32-byte width for L1-L2 bus
Andreas Hansson
2012-10-15
Stats: Update stats for use of two-level builder
Andreas Hansson
2012-10-15
Regression: Use addTwoLevelCacheHierarchy in configs
Andreas Hansson
2012-10-15
Clock: Inherit the clock from parent by default
Andreas Hansson
2012-10-15
Param: Fix proxy traversal to support chained proxies
Andreas Hansson
2012-10-15
Mem: Use range operations in bus in preparation for striping
Andreas Hansson
2012-10-11
Mem: Determine bus block size during initialisation
Andreas Hansson
2012-10-11
Doxygen: Update the version of the Doxyfile
Andreas Hansson
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